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IEICE Trans

Tatsuya KUNIKIYO

FOREWORD
Tatsuya KUNIKIYO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2018/05/01
Vol. E101-C  No. 5  pp. 303-304
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
 Summary | Full Text:PDF
FOREWORD
Tatsuya KUNIKIYO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2017/05/01
Vol. E100-C  No. 5  pp. 416-416
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
 Summary | Full Text:PDF
Exhaustive and Systematic Accuracy Verification and Enhancement of STI Stress Compact Model for General Realistic Layout Patterns
Kenta YAMADA Toshiyuki SYO Hisao YOSHIMURA Masaru ITO Tatsuya KUNIKIYO Toshiki KANAMOTO Shigetaka KUMASHIRO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/08/01
Vol. E93-C  No. 8  pp. 1349-1358
Type of Manuscript:  PAPER
Category: Semiconductor Materials and Devices
Keyword: 
STI, stress, model, verification, enhancement, 
 Summary | Full Text:PDF
A Method of Precise Estimation of Physical Parameters in LSI Interconnect Structures
Toshiki KANAMOTO Tetsuya WATANABE Mitsutoshi SHIROTA Masayuki TERAI Tatsuya KUNIKIYO Kiyoshi ISHIKAWA Yoshihide AJIOKA Yasutaka HORIBA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12  pp. 3463-3470
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Interconnect
Keyword: 
SoC, interconnect, physical parameter, low-k, capacitance, resistance, layout parasitic extraction, 
 Summary | Full Text:PDF
Realistic Scaling Scenario for Sub-100 nm Embedded SRAM Based on 3-Dimensional Interconnect Simulation
Yasumasa TSUKAMOTO Tatsuya KUNIKIYO Koji NII Hiroshi MAKINO Shuhei IWADE Kiyoshi ISHIKAWA Yasuo INOUE Norihiko KOTANI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/03/01
Vol. E86-C  No. 3  pp. 439-446
Type of Manuscript:  Special Section PAPER (Special Issue on the 2002 IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD'02))
Category: 
Keyword: 
embedded SRAM, scaling merit, 3-dimensional interconnect simulation, 50 and 70 nm technology nodes, 
 Summary | Full Text:PDF
3-D Topography and Impurity Integrated Process Simulator (3-D MIPS) and Its Applications
Masato FUJINAGO Tatsuya KUNIKIYO Tetsuya UCHIDA Eiji TSUKUDA Kenichiro SONODA Katsumi EIKYU Kiyoshi ISHIKAWA Tadashi NISHIMURA Satoru KAWAZU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/06/25
Vol. E82-C  No. 6  pp. 848-861
Type of Manuscript:  Special Section PAPER (Special Issue on TCAD for Semiconductor Industries)
Category: 
Keyword: 
LSI fabrication, process simulator, topography, impurity diffusion, segregation, capacitance, 
 Summary | Full Text:PDF
Nonlocal Impact Ionization Model and Its Application to Substrate Current Simulation of n-MOSFET's
Ken-ichiro SONODA Mitsuru YAMAJI Kenji TANIGUCHI Chihiro HAMAGUCHI Tatsuya KUNIKIYO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/03/25
Vol. E78-C  No. 3  pp. 274-280
Type of Manuscript:  Special Section PAPER (Special Issue on Sub-1/4 Micron Device and Process Technologies)
Category: 
Keyword: 
nonlocal impact ionization, substrate current, Monte Carlo simulation, device simulation, drift-diffusion model, 
 Summary | Full Text:PDF
Oblique Rotating Ion Implantation Simulation for the Drain Formation of Gate/N- Overlapped LDD MOSFET's Using the Monte Carlo Method
Tatsuya KUNIKIYO Masato FUJINAGA Tetsuya UCHIDA Norihiko KOTANI Yoichi AKASAKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1991/06/25
Vol. E74-C  No. 6  pp. 1662-1671
Type of Manuscript:  Special Section PAPER (Special Issue on Device and Process Simulation for Ultra Large Scale Integration)
Category: 
Keyword: 
 Summary | Full Text:PDF