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IEICE Trans

Takeshi OGURA

Development of Compression Tolerable and Highly Implementable Watermarking Method for Mobile Devices
Takeshi KUMAKI Kei NAKAO Kohei HOZUMI Takeshi OGURA Takeshi FUJINO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/03/01
Vol. E97-D  No. 3  pp. 593-596
Type of Manuscript:  LETTER
Category: Information Network
Keyword: 
watermark, max-plus algebra, morphological wavelet transform, JPEG, compression tolerance, mobile device, 
 Summary | Full Text:PDF
On-Chip Multimedia Real-Time OS and Its MPEG-2 Applications
Hiroe IWASAKI Jiro NAGANUMA Makoto ENDO Takeshi OGURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2001/04/01
Vol. E84-D  No. 4  pp. 448-455
Type of Manuscript:  PAPER
Category: VLSI Systems
Keyword: 
real-time OS, embedded system LSI (system LSI), multimedia processing, MPEG-2 systems, MPEG-2 video, 
 Summary | Full Text:PDF
Motion Estimation and Compensation Hardware Architecture for a Scene-Adaptive Algorithm on a Single-Chip MPEG-2 Video Encoder
Koyo NITTA Toshihiro MINAMI Toshio KONDO Takeshi OGURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2001/03/01
Vol. E84-D  No. 3  pp. 317-325
Type of Manuscript:  PAPER
Category: VLSI Systems
Keyword: 
motion estimation and compensation, scene-adaptive algorithm, MPEG-2 video encoder, hardware architecture, SIMD, 
 Summary | Full Text:PDF
Three-Layer Cooperative Architecture for MPEG-2 Video Encoder LSI
Mitsuo IKEDA Toshio KONDO Koyo NITTA Kazuhito SUGURI Takeshi YOSHITOME Toshihiro MINAMI Jiro NAGANUMA Takeshi OGURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2000/02/25
Vol. E83-C  No. 2  pp. 170-178
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Power High-Speed CMOS LSI Technologies)
Category: 
Keyword: 
MPEG-2, video signal processing, embedded system LSI, hardware/software co-design, picture coding, 
 Summary | Full Text:PDF
CAM-Based Highly-Parallel Image Processing Hardware
Takeshi OGURA Mamoru NAKANISHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/07/25
Vol. E80-C  No. 7  pp. 868-874
Type of Manuscript:  INVITED PAPER (Special Issue on New Concept Device and Novel Architecture LSIs)
Category: 
Keyword: 
content addressable memory, CAM, image processing, highly-parallel processing, 
 Summary | Full Text:PDF
A Distributed BIST Technique and Its Test Design Platrorm for VLSIs
Takeshi IKENAGA Takeshi OGURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/11/25
Vol. E78-C  No. 11  pp. 1618-1623
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
distributed built-in self-test, image processing LSI, pseudo random pattern generator, regular pattern, space compressor, 
 Summary | Full Text:PDF
High-Level VLSI Design Specification Validation Using Algorithmic Debugging
Jiro NAGANUMA Takeshi OGURA Tamio HOSHINO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/12/25
Vol. E77-A  No. 12  pp. 1988-1998
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
high-level design specification validation, structured analysis method, algorithmic debugging, logic programming languages, 
 Summary | Full Text:PDF