IEICE Trans

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IEICE Trans

Takeomi TAMESADA

Lead Open Detection Based on Supply Current of CMOS LSIs Masao TAKAGI Masaki HASHIZUME Masahiro ICHIMIYA Hiroyuki YOTSUYANAGI Takeomi TAMESADA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/06/01 Vol. E87-A No. 6 pp. 1330-1337 Type of Manuscript: Special Section PAPER (Special Section on Papers Selected from 2003 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2003)) Category: Keyword: lead open, CMOS LSI, supply current test, electric field,
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Genetic State Reduction Method of Incompletely Specified Machines Masaki HASHIZUME Teruyoshi MATSUSHIMA Takashi SHIMAMOTO Hiroyuki YOTSUYANAGI Takeomi TAMESADA Akio SAKAMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/06/01 Vol. E87-A No. 6 pp. 1555-1563 Type of Manuscript: PAPER Category: Graphs and Networks Keyword: incompletely specified machine, maximal compatible set, state reduction,
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Identification and Frequency Estimation of Feedback Bridging Faults Generating Logical Oscillation in CMOS Circuits Masaki HASHIZUME Hiroyuki YOTSUYANAGI Takeomi TAMESADA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2004/03/01 Vol. E87-D No. 3 pp. 571-579 Type of Manuscript: Special Section PAPER (Special Section on Test and Verification of VLSI) Category: Fault Detection Keyword: feedback bridging fault, combinational circuit, logical oscillation,
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Test Sequence Generation for Test Time Reduction of IDDQ Testing Hiroyuki YOTSUYANAGI Masaki HASHIZUME Takeomi TAMESADA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2004/03/01 Vol. E87-D No. 3 pp. 537-543 Type of Manuscript: Special Section PAPER (Special Section on Test and Verification of VLSI) Category: Test Generation and Compaction Keyword: IDDQ testing, bridging faults, switching current, supply current test, CMOS circuits,
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Test Pattern Generation for CMOS Open Defect Detection by Supply Current Testing under AC Electric Field Hiroyuki YOTSUYANAGI Taisuke IWAKIRI Masaki HASHIZUME Takeomi TAMESADA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2003/12/01 Vol. E86-D No. 12 pp. 2666-2673 Type of Manuscript: Special Section PAPER (Special Issue on Dependable Computing) Category: Test Keyword: open defects, supply current test, CMOS circuits, electric field,
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CMOS Open Defect Detection by Supply Current Measurement under Time-Variable Electric Field Supply Masaki HASHIZUME Masahiro ICHIMIYA Hiroyuki YOTSUYANAGI Takeomi TAMESADA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2002/10/01 Vol. E85-D No. 10 pp. 1542-1550 Type of Manuscript: Special Section PAPER (Special Issue on Test and Verification of VLSI) Category: Current Test Keyword: open defect, CMOS, supply current test, electric field,
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Sequential Redundancy Removal Using Test Generation and Multiple Strongly Unreachable States Hiroyuki YOTSUYANAGI Masaki HASHIZUME Takeomi TAMESADA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2002/10/01 Vol. E85-D No. 10 pp. 1605-1608 Type of Manuscript: Special Section LETTER (Special Issue on Test and Verification of VLSI) Category: Keyword: synthesis for testability, redundancy removal, sequential circuit, undetectable faults, unreachable states,
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Testable Static CMOS PLA for IDDQ Testing Masaki HASHIZUME Hiroshi HOSHIKA Hiroyuki YOTSUYANAGI Takeomi TAMESADA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/06/01 Vol. E84-A No. 6 pp. 1488-1495 Type of Manuscript: Special Section PAPER (Special Section on Papers Selected from 2000 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2000)) Category: Keyword: static PLA, testable design, IDDQ test, bridging fault,
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Heuristic State Reduction Methods of Incompletely Specified Machines Preceding to Satisfy Covering Condition Masaki HASHIZUME Takeomi TAMESADA Takashi SHIMAMOTO Akio SAKAMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/06/25 Vol. E81-A No. 6 pp. 1045-1054 Type of Manuscript: Special Section PAPER (Special Section of Papers Selected from ITC-CSCC'97) Category: VLSI Design Technology and CAD Keyword: incompletely specified machine, maximal compatible set, state reduction,
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A Practical Functional Test Using Flowchart for Production Testing of Microprocessor Based Sequence Controllers Masaki HASHIZUME Takeomi TAMESADA Eiji TASAKA Toshihiro KAYAHARA Tomohisa YAMAZOE
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1993/07/25 Vol. E76-D No. 7 pp. 837-841 Type of Manuscript: Special Section LETTER (Special Issue on VLSI Testing and Testable Design) Category: Keyword: sequence controller, process flowchart, functional test, microprocessor based circuit,
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Sequential Machines Having Quasi-Stable States and Their State Reduction Takeomi TAMESADA
Publication: IEICE TRANSACTIONS (1976-1990) Publication Date: 1981/03/25 Vol. E64-E No. 3 pp. 147-154 Type of Manuscript: PAPER Category: Digital Circuits Keyword:
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