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Region Oriented Routing FPGA Architecture for Dynamic Power Gating
Ce LI Yiping DONG Takahiro WATANABE | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A
No. 12
pp. 2199-2207
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Design
Keyword:
FPGA, low power, switch box, routing, | | | Summary | Full Text:PDF | |
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A New Recovery Mechanism in Superscalar Microprocessors by Recovering Critical Misprediction
Jiongyao YE Yu WAN Takahiro WATANABE | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A
No. 12
pp. 2639-2648
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword:
misprediction recovery, critical path prediction, trace cache, | | | Summary | Full Text:PDF | |
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Low Power Placement and Routing for the Coarse-Grained Power Gating FPGA Architecture
Ce LI Yiping DONG Takahiro WATANABE | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A
No. 12
pp. 2519-2527
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Design
Keyword:
FPGA, low power, power domain, power consumption, | | | Summary | Full Text:PDF | |
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Analog Layout Compaction with a Clean-up Function
Masahiro KAWAKITA Takahiro WATANABE | Publication: IEICE TRANSACTIONS (1976-1990)
Publication Date: 1988/12/25
Vol. E71-E
No. 12
pp. 1243-1252
Type of Manuscript:
Special Section PAPER (Special Issue on CAS Karuizawa Workshop)
Category:
Keyword:
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