Keyword : over-lapped clock


A Fine Grain Cooled Logic Architecture for Low-Power Processors
Hiroyuki MATSUBARA Takahiro WATANABE Tadao NAKAMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/03/01
Vol. E84-A  No. 3 ; pp. 735-740
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 13th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
low-powerpass transistordual-rail logicover-lapped clockCooled Logic
 Summary | Full Text:PDF

A Clocking Scheme for Lowering Peak-Current in Dynamic Logic Circuits
Hiroyuki MATSUBARA Takahiro WATANABE Tadao NAKAMURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2000/11/25
Vol. E83-C  No. 11 ; pp. 1733-1738
Type of Manuscript:  Special Section PAPER (Special Issue on Low-power LSIs and Technologies)
Category: 
Keyword: 
low-powerlevelingdynamic logicover-lapped clockpower control
 Summary | Full Text:PDF