Keyword : instruction cache


Analysis before Starting an Access: A New Power-Efficient Instruction Fetch Mechanism
Jiongyao YE Yingtao HU Hongfeng DING Takahiro WATANABE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2011/07/01
Vol. E94-D  No. 7 ; pp. 1398-1408
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
low powerinstruction cacheinstruction fetch mechanism
 Summary | Full Text:PDF

Adopting the Drowsy Technique for Instruction Caches: A Soft Error Perspective
Soong Hyun SHIN Sung Woo CHUNG Eui-Young CHUNG Chu Shik JHON 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/07/01
Vol. E91-A  No. 7 ; pp. 1772-1779
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
instruction cachesoft errordrowsy techniquelow-power
 Summary | Full Text:PDF

An Energy-Efficient Partitioned Instruction Cache Architecture for Embedded Processors
CheolHong KIM SungWoo CHUNG ChuShik JHON 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2006/04/01
Vol. E89-D  No. 4 ; pp. 1450-1458
Type of Manuscript:  PAPER
Category: Computer Systems
Keyword: 
instruction cachepartitioned cachelow power designdynamic energyembedded processor
 Summary | Full Text:PDF

Analytical Models and Performance Analyses of Instruction Fetch on Superscalar Processors
Sun-Mo KIM Jung-Woo LEE Soo-Haeng LEE Sang-Bang CHOI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/06/01
Vol. E84-A  No. 6 ; pp. 1442-1453
Type of Manuscript:  Special Section PAPER (Special Section on Papers Selected from 2000 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2000))
Category: 
Keyword: 
instruction cacheinstruction fetchanalytical modelsuperscalar processor
 Summary | Full Text:PDF