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IEICE Trans

Shigetoshi NAKATAKE

Density Optimization for Analog Layout Based on Transistor-Array
Chao GENG Bo LIU Shigetoshi NAKATAKE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2019/12/01
Vol. E102-A  No. 12  pp. 1720-1730
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
analog layout, manufacturability, layout density, transistor-array, 
 Summary | Full Text:PDF
A Low Voltage Stochastic Flash ADC without Comparator
Xuncheng ZOU Shigetoshi NAKATAKE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2019/07/01
Vol. E102-A  No. 7  pp. 886-893
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
low voltage, analog-to-digital converter, stochastic flash ADC, inverter-chain, Wallace tree adder, 
 Summary | Full Text:PDF
Low Voltage CMOS Current Mode Reference Circuit without Operational Amplifiers
Kenya KONDO Koichi TANNO Hiroki TAMURA Shigetoshi NAKATAKE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2018/05/01
Vol. E101-A  No. 5  pp. 748-754
Type of Manuscript:  PAPER
Category: Analog Signal Processing
Keyword: 
voltage reference, bandgap reference, current mode, OPAMP less, low voltage, low power, subthreshold, 
 Summary | Full Text:PDF
Subblock-Level Matching Layout for Analog Block-Pair and Its Layout-Dependent Manufacturability Evaluation
Takuya HIRATA Ryuta NISHINO Shigetoshi NAKATAKE Masaya SHIMOYAMA Masashi MIYAGAWA Ryoichi MIYAUCHI Koichi TANNO Akihiro YAMADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/07/01
Vol. E99-A  No. 7  pp. 1381-1389
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
instrumentation amplifier, layout-dependent manufacturability, analog layout, matching layout, 
 Summary | Full Text:PDF
A Sensor-Based Data Visualization System for Training Blood Pressure Measurement by Auscultatory Method
Chooi-Ling GOH Shigetoshi NAKATAKE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2016/04/01
Vol. E99-D  No. 4  pp. 936-943
Type of Manuscript:  Special Section PAPER (Special Section on Data Engineering and Information Management)
Category: 
Keyword: 
blood pressure measurement, auscultation, Korotkoff sounds, cuff pressure oscillation, data visualization, wireless sensor system, 
 Summary | Full Text:PDF
Layout Dependent Effect-Aware Leakage Current Reduction and Its Application to Low-Power SAR-ADC
Gong CHEN Yu ZHANG Qing DONG Ming-Yu LI Shigetoshi NAKATAKE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/07/01
Vol. E98-A  No. 7  pp. 1442-1454
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
leakage current reduction, layout dependent effect, low-power SAR-ADC, 
 Summary | Full Text:PDF
Analog Circuit Synthesis with Constraint Generation of Layout-Dependent Effects by Geometric Programming
Yu ZHANG Gong CHEN Bo YANG Jing LI Qing DONG Ming-Yu LI Shigetoshi NAKATAKE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/12/01
Vol. E96-A  No. 12  pp. 2487-2498
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Design
Keyword: 
circuit synthesis, STI, WPE, channel length modulation, geometric programming, 
 Summary | Full Text:PDF
Structured Analog Circuit and Layout Design with Transistor Array
Bo YANG Qing DONG Jing LI Shigetoshi NAKATAKE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/12/01
Vol. E96-A  No. 12  pp. 2475-2486
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Design
Keyword: 
transistor array, channel decomposition, structured analog design, manufacturability, 
 Summary | Full Text:PDF
Layout-Aware Variability Characterization of CMOS Current Sources
Bo LIU Bo YANG Shigetoshi NAKATAKE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/04/01
Vol. E95-C  No. 4  pp. 696-705
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
process variation, current mismatch, layout-dependent variation, analog DFM, 
 Summary | Full Text:PDF
Regularity-Oriented Analog Placement with Conditional Design Rules
Shigetoshi NAKATAKE Masahiro KAWAKITA Takao ITO Masahiro KOJIMA Michiko KOJIMA Kenji IZUMI Tadayuki HABASAKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/12/01
Vol. E93-A  No. 12  pp. 2389-2398
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Design
Keyword: 
analog placement, regularity-oriented, well-island, sequence-pair, 
 Summary | Full Text:PDF
Photomask Data Prioritization Based on VLSI Design Intent and Its Utilization for Mask Manufacturing
Kokoro KATO Masakazu ENDO Tadao INOUE Shigetoshi NAKATAKE Masaki YAMABE Sunao ISHIHARA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/12/01
Vol. E93-A  No. 12  pp. 2424-2432
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Device and Circuit Modeling and Analysis
Keyword: 
Mask Data Rank (MDR), design intent, DFM, MDP, 
 Summary | Full Text:PDF
Fast Shape Optimization of Metalization Patterns for Power-MOSFET Based Driver
Bo YANG Shigetoshi NAKATAKE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12  pp. 3052-3060
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Device and Circuit Modeling and Analysis
Keyword: 
power-MOSFET, metalization pattern, shape optimization, 
 Summary | Full Text:PDF
Incremental Buffer Insertion and Module Resizing Algorithm Using Geometric Programming
Qing DONG Bo YANG Jing LI Shigetoshi NAKATAKE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12  pp. 3103-3110
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verfication
Keyword: 
placement, floorplan, buffer insertion, module resizing, geometric programming, 
 Summary | Full Text:PDF
A Finite Element-Domain Decomposition Coupled Resistance Extraction Method with Virtual Terminal Insertion
Bo YANG Hiroshi MURATA Shigetoshi NAKATAKE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/02/01
Vol. E91-A  No. 2  pp. 542-549
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
DMOS, finite element method, domain decomposition, sub-domain reuse, resistance extraction, 
 Summary | Full Text:PDF
The Oct-Touched Tile: A New Architecture for Shape-Based Routing
Ning FU Shigetoshi NAKATAKE Yasuhiro TAKASHIMA Yoji KAJITANI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/02/01
Vol. E89-A  No. 2  pp. 448-455
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
analog layout, shape-based routing, routing architecture, tile, 
 Summary | Full Text:PDF
A Device-Level Placement with Schema Based Clusters in Analog IC Layouts
Takashi NOJIMA Xiaoke ZHU Yasuhiro TAKASHIMA Shigetoshi NAKATAKE Yoji KAJITANI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12  pp. 3301-3308
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Analog Layout
Keyword: 
device-level placement, rectangle packing, Sequence-Pair, directional convex, cluster-constraint, 
 Summary | Full Text:PDF
Abstraction and Optimization of Consistent Floorplanning with Pillar Block Constraints
Ning FU Shigetoshi NAKATAKE Yasuhiro TAKASHIMA Yoji KAJITANI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12  pp. 3224-3232
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Floorplan
Keyword: 
abstract floorplan, consistent floorplan, pillar, 
 Summary | Full Text:PDF
A Fast Algorithm for Crosspoint Assignment under Crosstalk Constraints with Shielding Effects
Keiji KIDA Xiaoke ZHU Changwen ZHUANG Yasuhiro TAKASHIMA Shigetoshi NAKATAKE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12  pp. 3258-3264
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Design
Keyword: 
crosspoint assignment (CPA), crosstalk, shielding effects, {d,1}-pitch constraint, maximum-cost-difference-assignment (MCDA), 
 Summary | Full Text:PDF
An Incremental Wiring Algorithm for VLSI Layout Design
Yukiko KUBO Shigetoshi NAKATAKE Yoji KAJITANI Masahiro KAWAKITA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/05/01
Vol. E86-A  No. 5  pp. 1203-1206
Type of Manuscript:  Special Section LETTER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
wirability, incremental wiring, channel intersection graph, wire decomposition, 
 Summary | Full Text:PDF
The 3D-Packing by Meta Data Structure and Packing Heuristics
Hiroyuki YAMAZAKI Keishi SAKANUSHI Shigetoshi NAKATAKE Yoji KAJITANI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/04/25
Vol. E83-A  No. 4  pp. 639-645
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
3D-packing, placement, sequence-pair, sequence-triple, simulated annealing, 
 Summary | Full Text:PDF