Incremental Buffer Insertion and Module Resizing Algorithm Using Geometric Programming

Jing LI
Shigetoshi NAKATAKE

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E92-A    No.12    pp.3103-3110
Publication Date: 2009/12/01
Online ISSN: 1745-1337
DOI: 10.1587/transfun.E92.A.3103
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verfication
placement,  floorplan,  buffer insertion,  module resizing,  geometric programming,  

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This paper presents an efficient algorithm for incremental buffer insertion and module resizing for a full-placed floorplan. Our algorithm offers a method to use the white space in a given floorplan to resize modules and insert buffers, and at the same time keeps the resultant floorplan as close to the original one as possible. Both the buffer insertion and module resizing are modeled as geometric programming problems, and can be solved extremely efficiently using new developed solution methods. The experimental results suggest that the the wire length difference between the initial floorplan and result are quite small (less than 5%), and the global structure of the initial floorplan are preserved very well.