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IEICE Trans

Seunghwan LEE

Highly-Parallel Stereo Vision VLSI Processor Based on an Optimal Parallel Memory Access Scheme
Masanori HARIYAMA Seunghwan LEE Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/03/01
Vol. E84-C  No. 3  pp. 382-389
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
motion stereo, memory allocation, functional-unit allocation, 
 Summary | Full Text:PDF
An FPGA-Oriented Motion-Stereo Processor with a Simple Interconnection Network for Parallel Memory Access
Seunghwan LEE Masanori HARIYAMA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2000/12/25
Vol. E83-D  No. 12  pp. 2122-2130
Type of Manuscript:  PAPER
Category: Image Processing, Image Pattern Recognition
Keyword: 
motion stereo, FPGA-based processor, memory allocation, functional unit allocation, 
 Summary | Full Text:PDF
A Three-Dimensional Instrumentation VLSI Processor Based on a Concurrent Memory-Access Scheme
Seunghwan LEE Masanori HARIYAMA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/11/25
Vol. E80-C  No. 11  pp. 1491-1498
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
3-D instrumentation, epipolar constraint, block matching algorithm, special-purpose VLSI processor, memory interleaving, 
 Summary | Full Text:PDF