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Through Chip Interface Based Three-Dimensional FPGA Architecture Exploration
Li-Chung HSU Masato MOTOMURA Yasuhiro TAKE Tadahiro KURODA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2015/04/01
Vol. E98-C
No. 4
pp. 288-297
Type of Manuscript:
Special Section PAPER (Special Section on Solid-State Circuit Design---Architecture, Circuit, Device and Design Methodology)
Category:
Keyword:
TCI, ThruChip, 3-D FPGA, TSV, FPGA, TPR, VPR, | | | Summary | Full Text:PDF | |
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On Reducing Test Power, Volume and Routing Cost by Chain Reordering and Test Compression Techniques
Chia-Yi LIN Li-Chung HSU Hung-Ming CHEN | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2010/03/01
Vol. E93-C
No. 3
pp. 369-378
Type of Manuscript:
Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
Category:
Keyword:
DFT, TSP, test power, | | | Summary | Full Text:PDF | |
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