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Kimihiko MASUDA

Test Scheduling for Multi-Clock Domain SoCs under Power Constraint Tomokazu YONEDA Kimihiko MASUDA Hideo FUJIWARA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2008/03/01 Vol. E91-D No. 3 pp. 747-755 Type of Manuscript: Special Section PAPER (Special Section on Test and Verification of VLSIs) Category: High-Level Testing Keyword: multi-clock domain SoC, test scheduling, test access mechanism, power consumption,
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