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IEICE Trans

Kenichi ICHINO


Application of Partially Rotational Scan Technique with Tester IP for Processor Circuits
Kenichi ICHINO Ko-ichi WATANABE Masayuki ARAI Satoshi FUKUMOTO Kazuhiko IWASAKI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/03/01
Vol. E87-D  No. 3  pp. 586-591
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSI)
Category: Scan Testing
Keyword: 
hybrid BIST, n-detection test, partially rotational scan, low-speed tester, 
 Summary | Full Text:PDF

Seed Selection Procedure for LFSR-Based Random Pattern Generators
Kenichi ICHINO Ko-ichi WATANABE Masayuki ARAI Satoshi FUKUMOTO Kazuhiko IWASAKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12  pp. 3063-3071
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Timing Verification and Test Generation
Keyword: 
BIST, LFSR, test-per-clock, test-per-scan, seed, polynomial, 
 Summary | Full Text:PDF

Hybrid BIST Design for n-Detection Test Using Partially Rotational Scan
Kenichi ICHINO Takeshi ASAKAWA Satoshi FUKUMOTO Kazuhiko IWASAKI Seiji KAJIHARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/10/01
Vol. E85-D  No. 10  pp. 1490-1497
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Verification of VLSI)
Category: BIST
Keyword: 
hybrid BIST, unmodeled fault, n-detection test, partially rotational scan, at-speed testing, 
 Summary | Full Text:PDF