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IEICE Trans

Keisuke INOUE

Dual-Edge-Triggered Flip-Flop-Based High-Level Synthesis with Programmable Duty Cycle
Keisuke INOUE Mineo KANEKO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/12/01
Vol. E96-A  No. 12  pp. 2689-2697
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
dual-edge-triggered flip-flop, programmable duty cycle, operation scheduling, MILP, high-level synthesis, 
 Summary | Full Text:PDF
Heuristic and Exact Resource Binding Algorithms for Storage Optimization Using Flip-Flops and Latches
Keisuke INOUE Mineo KANEKO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/08/01
Vol. E96-A  No. 8  pp. 1712-1722
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
flip-flop/latch-based design, high-level synthesis, resource binding, storage-type selection, 
 Summary | Full Text:PDF
A Formal Approach to Optimal Register Binding with Ordered Clocking for Clock-Skew Tolerant Datapaths
Keisuke INOUE Mineo KANEKO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A  No. 12  pp. 2330-2337
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
clock-skew, ordered clocking, high-level synthesis, 
 Summary | Full Text:PDF
Backward-Data-Direction Clocking and Relevant Optimal Register Assignment in Datapath Synthesis
Keisuke INOUE Mineo KANEKO Tsuyoshi IWAGAKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/04/01
Vol. E94-A  No. 4  pp. 1067-1081
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
datapath synthesis, delay variation, register assignment, hold timing constraint, backward-data-direction clocking, integer linear programming, 
 Summary | Full Text:PDF
Optimal Register Assignment with Minimum-Path Delay Compensation for Variation-Aware Datapaths
Keisuke INOUE Mineo KANEKO Tsuyoshi IWAGAKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/04/01
Vol. E92-A  No. 4  pp. 1096-1105
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Technologies Emerging Mainly from the 21st Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
datapath synthesis, delay variation, register assignment, setup and hold constraints, minimum delay compensation, integer linear programming, 
 Summary | Full Text:PDF
Novel Register Sharing in Datapath for Structural Robustness against Delay Variation
Keisuke INOUE Mineo KANEKO Tsuyoshi IWAGAKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/04/01
Vol. E91-A  No. 4  pp. 1044-1053
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 20th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
datapath synthesis, delay variation, register assignment, setup and hold constraints, 
 Summary | Full Text:PDF