IEICE Trans

Keyword : integer linear programming

A Petri Net Approach to Generate Integer Linear Programming Problems Morikazu NAKAMURA Takeshi TENGAN Takeo YOSHIDA
Publication: Publication Date: 2019/02/01 Vol. E102-A No. 2 ; pp. 389-398 Type of Manuscript: Special Section PAPER (Special Section on Mathematical Systems Science and its Applications) Category: Keyword: mathematical programming, integer linear programming, Petri net, colored timed Petri net, autonomous Petri net,
	Summary \| Full Text:PDF

Cloud Provider Selection Models for Cloud Storage Services to Satisfy Availability Requirements Eiji OKI Ryoma KANEKO Nattapong KITSUWAN Takashi KURIMOTO Shigeo URUSHIDANI
Publication: Publication Date: 2017/08/01 Vol. E100-B No. 8 ; pp. 1406-1418 Type of Manuscript: PAPER Category: Network Keyword: cloud storage, availability, service requirement, optimization, integer linear programming,
	Summary \| Full Text:PDF

Static Mapping of Parallelizable Tasks under Deadline Constraints Yining XU Ittetsu TANIGUCHI Hiroyuki TOMIYAMA
Publication: Publication Date: 2017/07/01 Vol. E100-A No. 7 ; pp. 1500-1502 Type of Manuscript: Special Section LETTER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: task mapping, manycore embedded systems, integer linear programming,
	Summary \| Full Text:PDF

Trip-Based Integer Linear Programming Model for Static Multi-Car Elevator Operation Problems Tsutomu INAMOTO Yoshinobu HIGAMI Shin-ya KOBAYASHI
Publication: Publication Date: 2017/02/01 Vol. E100-A No. 2 ; pp. 385-394 Type of Manuscript: Special Section PAPER (Special Section on Mathematical Systems Science and its Applications) Category: Keyword: elevator operation problem, multi-car elevator system, integer linear programming, interference prevention,
	Summary \| Full Text:PDF

Technology Mapping Method Using Integer Linear Programming for Low Power Consumption and High Performance in General-Synchronous Framework Junki KAWAGUCHI Hayato MASHIKO Yukihide KOHIRA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2016/07/01 Vol. E99-A No. 7 ; pp. 1366-1373 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: general-synchronous framework, technology mapping, integer linear programming,
	Summary \| Full Text:PDF

Area-Efficient Soft-Error Tolerant Datapath Synthesis Based on Speculative Resource Sharing Junghoon OH Mineo KANEKO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2016/07/01 Vol. E99-A No. 7 ; pp. 1311-1322 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: speculative resource sharing, soft-error, fault tolerant datapath, triple algorithm redundancy, high-level synthesis, integer linear programming,
	Summary \| Full Text:PDF

Static Mapping of Multiple Parallel Applications on Non-Hierarchical Manycore Embedded Systems Yining XU Yang LIU Junya KAIDA Ittetsu TANIGUCHI Hiroyuki TOMIYAMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2016/07/01 Vol. E99-A No. 7 ; pp. 1417-1419 Type of Manuscript: Special Section LETTER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: application mapping, manycore embedded systems, integer linear programming,
	Summary \| Full Text:PDF

Optimum Route Design in 1+1 Protection with Network Coding for Instantaneous Recovery Abu Hena Al MUKTADIR Eiji OKI
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2014/01/01 Vol. E97-B No. 1 ; pp. 87-104 Type of Manuscript: PAPER Category: Internet Keyword: routing, network coding, 1+1 protection, integer linear programming, heuristic algorithm,
	Summary \| Full Text:PDF

An Exact Approach for GPC-Based Compressor Tree Synthesis Taeko MATSUNAGA Shinji KIMURA Yusuke MATSUNAGA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2013/12/01 Vol. E96-A No. 12 ; pp. 2553-2560 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verification Keyword: compressor tree, generalized parallel counter, integer linear programming, arithmetic synthesis,
	Summary \| Full Text:PDF

Flexible Test Scheduling for an Asynchronous On-Chip Interconnect through Special Data Transfer Tsuyoshi IWAGAKI Eiri TAKEDA Mineo KANEKO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/12/01 Vol. E94-A No. 12 ; pp. 2563-2570 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verification Keyword: asynchronous on-chip interconnect, CHAIN, stuck-at fault, test scheduling, integer linear programming,
	Summary \| Full Text:PDF

Wire Planning for Electromigration and Interference Avoidance in Analog Circuits Hsin-Hsiung HUANG Jui-Hung HUNG Cheng-Chiang LIN Tsai-Ming HSIEH
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/11/01 Vol. E94-A No. 11 ; pp. 2402-2411 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: analog circuits, wire planning with obstacles, electromigration, interference, integer linear programming,
	Summary \| Full Text:PDF

Backward-Data-Direction Clocking and Relevant Optimal Register Assignment in Datapath Synthesis Keisuke INOUE Mineo KANEKO Tsuyoshi IWAGAKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/04/01 Vol. E94-A No. 4 ; pp. 1067-1081 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: datapath synthesis, delay variation, register assignment, hold timing constraint, backward-data-direction clocking, integer linear programming,
	Summary \| Full Text:PDF

Optimal Supply Voltage Assignment under Timing, Power and Area Constraints Hsi-An CHIEN Cheng-Chiang LIN Hsin-Hsiung HUANG Tsai-Ming HSIEH
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/04/01 Vol. E93-A No. 4 ; pp. 761-768 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: level shifter, multiple supply voltage, low power, voltage assignment, integer linear programming,
	Summary \| Full Text:PDF

Power Minimization for Dual- and Triple-Supply Digital Circuits via Integer Linear Programming Ki-Yong AHN Chong-Min KYUNG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/09/01 Vol. E92-A No. 9 ; pp. 2318-2325 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: system on chip, low power design, partitioning, integer linear programming,
	Summary \| Full Text:PDF

Optimal Register Assignment with Minimum-Path Delay Compensation for Variation-Aware Datapaths Keisuke INOUE Mineo KANEKO Tsuyoshi IWAGAKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/04/01 Vol. E92-A No. 4 ; pp. 1096-1105 Type of Manuscript: Special Section PAPER (Special Section on Advanced Technologies Emerging Mainly from the 21st Workshop on Circuits and Systems in Karuizawa) Category: Keyword: datapath synthesis, delay variation, register assignment, setup and hold constraints, minimum delay compensation, integer linear programming,
	Summary \| Full Text:PDF

Optimization for Optical Network Designs Based on Existing Power Grids Areeyata SRIPETCH Poompat SAENGUDOMLERT
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2008/03/01 Vol. E91-B No. 3 ; pp. 689-699 Type of Manuscript: PAPER Category: Optical Fiber for Communications Keyword: physical topology design, routing and wavelength assignment, optical amplifier placement, integer linear programming, simulated annealing,
	Summary \| Full Text:PDF

An ILP Approach to the Simultaneous Application of Operation Scheduling and Power Management Shih-Hsu HUANG Chun-Hua CHENG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/01/01 Vol. E91-A No. 1 ; pp. 375-382 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: high-level synthesis, integer linear programming, scheduling, low power,
	Summary \| Full Text:PDF

A Simultaneous Module Selection, Scheduling, and Allocation Method Considering Operation Chaining with Multi-Functional Units Tsuyoshi SADAKATA Yusuke MATSUNAGA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/04/01 Vol. E90-A No. 4 ; pp. 792-799 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: high-level synthesis, scheduling, allocation, module selection, operation chaining, integer linear programming,
	Summary \| Full Text:PDF

An ILP Approach to the Slack Driven Scheduling Problem Shih-Hsu HUANG Chun-Hua CHENG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/06/01 Vol. E89-A No. 6 ; pp. 1852-1858 Type of Manuscript: LETTER Category: VLSI Design Technology and CAD Keyword: high-level synthesis, integer linear programming, scheduling, slack optimization,
	Summary \| Full Text:PDF

Cell Library Development Methodology for Throughput Enhancement of Character Projection Equipment Makoto SUGIHARA Taiga TAKATA Kenta NAKAMURA Ryoichi INANAMI Hiroaki HAYASHI Katsumi KISHIMOTO Tetsuya HASEBE Yukihiro KAWANO Yusuke MATSUNAGA Kazuaki MURAKAMI Katsuya OKUMURA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/03/01 Vol. E89-C No. 3 ; pp. 377-383 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era) Category: CAD Keyword: cell library, character projection, electron beam, EB shots, throughput, optimization, integer linear programming,
	Summary \| Full Text:PDF

Analysis and Design of Multicast Routing and Wavelength Assignment in Mesh and Multi-Ring WDM Transport Networks with Multiple Fiber Systems Charoenchai BOWORNTUMMARAT Lunchakorn WUTTISITTIKULKIJ Sak SEGKHOONTHOD
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2004/11/01 Vol. E87-B No. 11 ; pp. 3216-3229 Type of Manuscript: PAPER Category: Network Keyword: multicast routing and wavelength assignment, mesh design, multi-ring design, light-tree, fanout, integer linear programming, lower bound, network connectivity,
	Summary \| Full Text:PDF

Resource-Optimal Software Pipelining Using Flow Graphs Dirk FIMMEL Jan MULLER Renate MERKER
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2003/09/01 Vol. E86-D No. 9 ; pp. 1560-1568 Type of Manuscript: INVITED PAPER (Special Issue on Parallel and Distributed Computing, Applications and Technologies) Category: Software Systems and Technologies Keyword: software pipelining, instruction level parallelism, integer linear programming, resource constraints, heterogeneous architectures,
	Summary \| Full Text:PDF

Design of Reconfigurable Lightpaths in IP over WDM Networks Hiroaki HARAI Fumito KUBOTA Hidenori NAKAZATO
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2000/10/25 Vol. E83-B No. 10 ; pp. 2234-2244 Type of Manuscript: Special Section PAPER (Special Issue on Advanced Internetworking based on Photonic Network Technologies) Category: Keyword: IP over WDM network, network design, lightpath configuration, integer linear programming, MPLS,
	Summary \| Full Text:PDF

ILIN: An Implementation of the Integer Labeling Algorithm for Integer Programming Qiang LI Fred JANSSEN Zaifu YANG Tetsuo IDA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/02/25 Vol. E81-A No. 2 ; pp. 304-309 Type of Manuscript: PAPER Category: Numerical Analysis and Optimization Keyword: simplex, integer point, integer labeling algorithm, integer linear programming,
	Summary \| Full Text:PDF

An Optimal Block Terminal Assignment Algorithm for VLSI Data Path Allocation Shoichiro YAMADA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/03/25 Vol. E80-A No. 3 ; pp. 564-566 Type of Manuscript: Special Section LETTER (Special Section of Selected Papers from the 9th Karuizawa Workshop on Circuits and Systems) Category: Keyword: block terminal assignment, data path allocation, high-level synthesis, integer linear programming,
	Summary \| Full Text:PDF

A Scheduling Method Using Boolean Equations in High-Level Synthesis Toshiaki MIYAZAKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1992/12/25 Vol. E75-A No. 12 ; pp. 1728-1731 Type of Manuscript: Special Section LETTER (Special Section on the 1992 IEICE Fall Conference) Category: Keyword: integer linear programming, BDD, data path,
	Summary \| Full Text:PDF