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| Jing-Yang JOU
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A New Method for Constructing IP Level Power Model Based on Power Sensitivity
Heng-Liang HUANG Jiing-Yuan LIN Wen-Zen SHEN Jing-Yang JOU | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A
No. 12
pp. 2431-2438
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Design Methodology
Keyword:
IP, power model, power sensitivity, | | | Summary | Full Text:PDF | |
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Internet-Based Hierarchical Floorplan Design
Jiann-Horng LIN Jing-Yang JOU Iris Hui-Ru JIANG | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/25
Vol. E82-A
No. 11
pp. 2414-2423
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category:
Keyword:
internet, floorplanning, | | | Summary | Full Text:PDF | |
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