A Variable Partitioning Algorithm of BDD for FPGA Technology Mapping

Jie-Hong JIANG
Jing-Yang JOU
Juinn-Dar HUANG
Jung-Shian WEI

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E80-A    No.10    pp.1813-1819
Publication Date: 1997/10/25
Online ISSN: 
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
binary decision diagrams,  equivalent class,  Roth-Karp decomposition,  LUT-based FPGA,  

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Field Programmable Gate Arrays (FPGA's) are important devices for rapid system prototyping. Roth-Karp decomposition is one of the most popular decomposition techniques for Look-Up Table (LUT) -based FPGA technology mapping. In this paper, we propose a novel algorithm based on Binary Decision Diagrams (BDD's) for selecting good lambda set variables in Roth-Karp decomposition to minimize the number of consumed configurable logic blocks (CLB's) in FPGA's. The experimental results on a set of benchmarks show that our algorithm can produce much better results than the similar works of the previous approaches.