Chia-I CHEN


Performance-Driven Architectural Synthesis for Distributed Register-File Microarchitecture with Inter-Island Delay
Juinn-Dar HUANG Chia-I CHEN Wan-Ling HSU Yen-Ting LIN Jing-Yang JOU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/02/01
Vol. E95-A  No. 2  pp. 559-566
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
Behavioral synthesisdistributed register-fileperformance optimizationlow-powerresource bindingscheduling
 Summary | Full Text:PDF

Communication Synthesis for Interconnect Minimization Targeting Distributed Register-File Microarchitecture
Juinn-Dar HUANG Chia-I CHEN Yen-Ting LIN Wan-Ling HSU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/04/01
Vol. E94-A  No. 4  pp. 1151-1155
Type of Manuscript:  LETTER
Category: VLSI Design Technology and CAD
Keyword: 
communication synthesisdistributed register-file microarchitectureinterconnect minimizationresource bindingscheduling
 Summary | Full Text:PDF

A Hierarchical Criticality-Aware Architectural Synthesis Framework for Multicycle Communication
Chia-I CHEN Juinn-Dar HUANG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/07/01
Vol. E93-A  No. 7  pp. 1300-1308
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
multicycle communicationarchitectural synthesishigh-level synthesisperformance-drivencriticality-driven
 Summary | Full Text:PDF