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IEICE Trans

Hiroyuki KUNISHIMA

Chip-Level Performance Maximization Using ASIS (Application-Specific Interconnect Structure) Wiring Design Concept for 45 nm CMOS Generation
Noriaki ODA Hironori IMURA Naoyoshi KAWAHARA Masayoshi TAGAMI Hiroyuki KUNISHIMA Shuji SONE Sadayuki OHNISHI Kenta YAMADA Yumi KAKUHARA Makoto SEKINE Yoshihiro HAYASHI Kazuyoshi UENO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/04/01
Vol. E90-C  No. 4  pp. 848-855
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies)
Category: Device
Keyword: 
copper, low-k, CMOS, interconnect, design, application, 
 Summary | Full Text:PDF
Chip-Level Performance Improvement Using Triple Damascene Wiring Design Concept for the 0.13 µm CMOS Generation and Beyond
Noriaki ODA Hiroyuki KUNISHIMA Takashi KYOUNO Kazuhiro TAKEDA Tomoaki TANAKA Toshiyuki TAKEWAKI Masahiro IKEDA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/11/01
Vol. E89-C  No. 11  pp. 1544-1550
Type of Manuscript:  Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies)
Category: 
Keyword: 
copper, CMOS, damascene, design, 
 Summary | Full Text:PDF