Kazuhiro TAKEDA


Chip-Level Performance Improvement Using Triple Damascene Wiring Design Concept for the 0.13 µm CMOS Generation and Beyond
Noriaki ODA Hiroyuki KUNISHIMA Takashi KYOUNO Kazuhiro TAKEDA Tomoaki TANAKA Toshiyuki TAKEWAKI Masahiro IKEDA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/11/01
Vol. E89-C  No. 11  pp. 1544-1550
Type of Manuscript:  Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies)
Category: 
Keyword: 
copperCMOSdamascenedesign
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