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IEICE Trans

Hiroshi YUASA

Parallel Acceleration Scheme for Monte Carlo Based SSTA Using Generalized STA Processing Element
Hiroshi YUASA Hiroshi TSUTSUI Hiroyuki OCHI Takashi SATO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/04/01
Vol. E96-C  No. 4  pp. 473-481
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
statistical static timing analysis, delay distribution, slew rate, field-programmable gate array, Mersenne Twister, 
 Summary | Full Text:PDF