Parallel Acceleration Scheme for Monte Carlo Based SSTA Using Generalized STA Processing Element

Hiroshi YUASA
Hiroyuki OCHI
Takashi SATO

IEICE TRANSACTIONS on Electronics   Vol.E96-C    No.4    pp.473-481
Publication Date: 2013/04/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E96.C.473
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology)
statistical static timing analysis,  delay distribution,  slew rate,  field-programmable gate array,  Mersenne Twister,  

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We propose a novel acceleration scheme for Monte Carlo based statistical static timing analysis (MC-SSTA). MC-SSTA, which repeatedly executes ordinary STA using a set of randomly generated gate delay samples, is widely accepted as an accuracy reference. A large number of random samples, however, should be processed to obtain accurate delay distributions, and software implementation of MC-SSTA, therefore, takes an impractically long processing time. In our approach, a generalized hardware module, the STA processing element (STA-PE), is used for the delay evaluation of a logic gate, and netlist-specific information is delivered in the form of instructions from an SRAM. Multiple STA-PEs can be implemented for parallel processing, while a larger netlist can be handled if only a larger SRAM area is available. The proposed scheme is successfully implemented on Altera's Arria II GX EP2AGX125EF35C4 device in which 26 STA-PEs and a 624-port Mersenne Twister-based random number generator run in parallel at a 116 MHz clock rate. A speedup of far more than10 is achieved compared to conventional methods including GPU implementation.