Keyword : field-programmable gate array


An Implementation of Multiple-Standard Video Decoder on a Mixed-Grained Reconfigurable Computing Platform
Leibo LIU Dong WANG Yingjie CHEN Min ZHU Shouyi YIN Shaojun WEI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2016/05/01
Vol. E99-D  No. 5 ; pp. 1285-1295
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
algorithm mappingcoarse-grained reconfigurable arrayfield-programmable gate arrayreconfigurable computingvideo decoding
 Summary | Full Text:PDF

Parallel Acceleration Scheme for Monte Carlo Based SSTA Using Generalized STA Processing Element
Hiroshi YUASA Hiroshi TSUTSUI Hiroyuki OCHI Takashi SATO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/04/01
Vol. E96-C  No. 4 ; pp. 473-481
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
statistical static timing analysisdelay distributionslew ratefield-programmable gate arrayMersenne Twister
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An Efficient FPGA Technology Mapping Tightly Coupled with Logic Minimization
Kang YI Seong Yong OHM Chu Shik JHON 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/10/25
Vol. E80-A  No. 10 ; pp. 1807-1812
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
logic synthesistechnology mappinglogic minimizationBoolean networkfield-programmable gate array
 Summary | Full Text:PDF

ASAver.1: An FPGA-Based Education Board for Computer Architecture/System Design
Hiroyuki OCHI Yoko KAMIDOI Hideyuki KAWABATA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/10/25
Vol. E80-A  No. 10 ; pp. 1826-1833
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
education of computer architecturesystem designDLX-like pipelined RISC processorfield-programmable gate arrayverilog-HDL
 Summary | Full Text:PDF