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IEICE Trans

Chu Shik JHON

Write Avoidance Cache Coherence Protocol for Non-volatile Memory as Last-Level Cache in Chip-Multiprocessor
Ju Hee CHOI Jong Wook KWAK Chu Shik JHON 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/08/01
Vol. E97-D  No. 8  pp. 2166-2169
Type of Manuscript:  LETTER
Category: Computer System
Keyword: 
cache coherence, non volatile memory, STT-RAM, chip multi-processor, 
 Summary | Full Text:PDF
Data Filter Cache with Partial Tag Matching for Low Power Embedded Processor
Ju Hee CHOI Jong Wook KWAK Seong Tae JHANG Chu Shik JHON 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/04/01
Vol. E97-D  No. 4  pp. 972-975
Type of Manuscript:  LETTER
Category: Computer System
Keyword: 
filter cache, L0 cache, data cache, partial tag, partial address, 
 Summary | Full Text:PDF
Throttling Capacity Sharing Using Life Time and Reuse Time Prediction in Private L2 Caches of Chip Multiprocessors
Young-Sik EOM Jong Wook KWAK Seong Tae JHANG Chu Shik JHON 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/06/01
Vol. E95-D  No. 6  pp. 1676-1679
Type of Manuscript:  LETTER
Category: Computer System
Keyword: 
Chip Multi-Processors, private L2 cache, capacity sharing, cooperative caching, 
 Summary | Full Text:PDF
Adopting the Drowsy Technique for Instruction Caches: A Soft Error Perspective
Soong Hyun SHIN Sung Woo CHUNG Eui-Young CHUNG Chu Shik JHON 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/07/01
Vol. E91-A  No. 7  pp. 1772-1779
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
instruction cache, soft error, drowsy technique, low-power, 
 Summary | Full Text:PDF
Robust Delay Control for Audio Streaming over Wireless Link
Hyo Jin CHOI Jinhwan JEON Taehyoun KIM Hyo-Joong SUH Chu Shik JHON 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2006/08/01
Vol. E89-D  No. 8  pp. 2448-2451
Type of Manuscript:  LETTER
Category: Networks
Keyword: 
delay control, wireless audio streaming, frame sequence adaptation, sampling frequency compensation, 
 Summary | Full Text:PDF
The Impact of Branch Direction History Combined with Global Branch History in Branch Prediction
Jong Wook KWAK Ju-Hwan KIM Chu Shik JHON 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/07/01
Vol. E88-D  No. 7  pp. 1754-1758
Type of Manuscript:  LETTER
Category: Computer Systems
Keyword: 
branch prediction, Branch Direction History, Global Branch History, gshare predictor, direction-gshare predictor, 
 Summary | Full Text:PDF
Torus Ring: Improving Interconnection Network Performance by Modifying Hierarchical Ring
Jong Wook KWAK Hyong Jin BAN Chu Shik JHON 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/05/01
Vol. E88-D  No. 5  pp. 1067-1071
Type of Manuscript:  LETTER
Category: Computer Systems
Keyword: 
multiprocessor system, interconnection network, hierarchical ring, Torus Ring, network topology, 
 Summary | Full Text:PDF
Utilization of the On-Chip L2 Cache Area in CC-NUMA Multiprocessors for Applications with a Small Working Set
Sung Woo CHUNG Hyong-Shik KIM Chu Shik JHON 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/07/01
Vol. E87-D  No. 7  pp. 1617-1624
Type of Manuscript:  Special Section PAPER (Special Section on Hardware/Software Support for High Performance Scientific and Engineering Computing)
Category: Networking and System Architectures
Keyword: 
CC-NUMA multiprocessor, cache replacement policy, on-chip cache, remote victim cache, distance-aware cache, interconnection network, 
 Summary | Full Text:PDF
An Efficient Method of Eliminating Inclusion Overhead in Snoop-Based CC-NUMA Systems
Hyo-Joong SUH Seung Wha YOO Chu Shik JHON 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2000/02/25
Vol. E83-D  No. 2  pp. 159-167
Type of Manuscript:  PAPER
Category: Computer Systems
Keyword: 
multi-level cache inclusion property, snoopy protocol, CC-NUMA, 
 Summary | Full Text:PDF
Selective Write-Update: A Method to Relax Execution Constraints in a Critical Section
Jae Bum LEE Chu Shik JHON 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/11/25
Vol. E81-D  No. 11  pp. 1186-1194
Type of Manuscript:  PAPER
Category: Computer Systems
Keyword: 
shared-memory multiprocessors, cache coherency, write policy, write cache, release consistency, QOLB, 
 Summary | Full Text:PDF
An Efficient FPGA Technology Mapping Tightly Coupled with Logic Minimization
Kang YI Seong Yong OHM Chu Shik JHON 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/10/25
Vol. E80-A  No. 10  pp. 1807-1812
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
logic synthesis, technology mapping, logic minimization, Boolean network, field-programmable gate array, 
 Summary | Full Text:PDF
An Optimal Scheduling Approach Using Lower Bound in High-Level Synthesis
Seong Yong OHM Fadi J. KURDAHI Chu Shik JHON 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/03/25
Vol. E78-D  No. 3  pp. 231-236
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: High-Level Synthesis
Keyword: 
high-level synthesis, scheduling, lower bound estimation, 
 Summary | Full Text:PDF