Throttling Capacity Sharing Using Life Time and Reuse Time Prediction in Private L2 Caches of Chip Multiprocessors

Young-Sik EOM  Jong Wook KWAK  Seong Tae JHANG  Chu Shik JHON  

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E95-D   No.6   pp.1676-1679
Publication Date: 2012/06/01
Online ISSN: 1745-1361
DOI: 10.1587/transinf.E95.D.1676
Print ISSN: 0916-8532
Type of Manuscript: LETTER
Category: Computer System
Keyword: 
Chip Multi-Processors,  private L2 cache,  capacity sharing,  cooperative caching,  

Full Text: PDF>>
Buy this Article




Summary: 
In Chip Multi-Processors (CMPs), private L2 caches have potential benefits in future CMPs, e.g. small access latency, performance isolation, tile-friendly architecture and simple low bandwidth on-chip interconnect. But the major weakness of private cache is the higher cache miss rate caused by small private cache capacity. To deal with this problem, private caches can share capacity through spilling replaced blocks to other private caches. However, indiscriminate spilling can make capacity problem worse and influence performance negatively. This letter proposes throttling capacity sharing (TCS) for effective capacity sharing in private L2 caches. TCS determines whether to spill a replaced block by predicting reuse possibility, based on life time and reuse time. In our performance evaluation, TCS improves weighted speedup by 48.79%, 6.37% and 5.44% compared to non-spilling, Cooperative Caching with best spill probability (CC) and Dynamic Spill-Receive (DSR), respectively.