|
Vol.E74-B No.11
pp.3733-3737
PAPER
Optical Communication
Relations between Inter-Modulation Distortion and Laser Diodes Characteristics in 42 Channels Optical AM Transmission
Fumihide HATTORI, Kazunori SHIRAISHI, Nobuo SHIGENO, Koichi GEN-EI, Koyu CHINEN, |
|
Summary | Full Text:PDF | |
|
Vol.E74-B No.11
pp.3738-3739
LETTER
Antennas and Propagation
A High Efficiency Slotted Array for DBS Reception Using a Copper Clad Laminates
Makoto ANDO, Naohisa GOTO, |
|
Summary | Full Text:PDF | |
|
Vol.E74-C No.11
pp.3747-3748
FOREWORD
FOREWORD
Osamu TOMISAWA, |
|
Summary | Full Text:PDF | |
|
Vol.E74-C No.11
pp.3749-3756
Special SectionPAPER
Circuit Design
A Master Chip Design of 0.5 µm Mixed BiCMOS/CMOS Channelless Gate Array Family
Yoji NISHIO, Noriaki OKA, Shigeru TAKAHASHI, Manabu SHIBATA, |
|
Summary | Full Text:PDF | |
|
Vol.E74-C No.11
pp.3757-3765
Special SectionPAPER
Circuit Design
Self-Timed Clocking Design for a Data-Driven Microprocessor
Fumiyasu ASAI, Shinji KOMORI, Toshiyuki TAMURA, Hisakazu SATO, Hidehiro TAKATA, Yoshihiro SEGUCHI, Takeshi TOKUDA, Hiroaki TERADA, |
|
Summary | Full Text:PDF | |
|
Vol.E74-C No.11
pp.3766-3774
Special SectionPAPER
Core and Macrocells
A High Performance 32-Bit Microcontroller for Realtime Applications
Masafumi TAKAHASHI, Yasuo YAMADA, Emi KANEKO, Shinichi YOSHIOKA, Haruyuki TAGO, |
|
Summary | Full Text:PDF | |
|
Vol.E74-C No.11
pp.3775-3779
Special SectionPAPER
Core and Macrocells
A 64 b CMOS Mainframe Execution Unit Macrocell with Error Detecting Circuit
Takehisa HAYASHI, Toshio DOI, Mikio YAMAGISHI, Kazuo KOIDE, Akira ISHIYAMA, Masataka HIRAMATSU, Akira YAMAGIWA, |
|
Summary | Full Text:PDF | |
|
Vol.E74-C No.11
pp.3780-3786
Special SectionPAPER
Core and Macrocells
A 5 ns Embedded RAM for CMOS ASICs and Its Applications to a One-Chip 4096-Channel Time Switch VLSI for Digital Switching Systems
Masao MIZUKAMI, Yasuo MIKAMI, Osamu MATSUBARA, Yoichi SATOH, Koichi SUDOH, |
|
Summary | Full Text:PDF | |
|
Vol.E74-C No.11
pp.3787-3795
Special SectionPAPER
Core and Macrocells
A High-Performance Reconfigurable Line Memory Macrocell for Video Signal Processing ASICs
Tetsuya MATSUMURA, Masahiko YOSHIMOTO, Atsushi MAEDA, Yasutaka HORIBA, |
|
Summary | Full Text:PDF | |
|
Vol.E74-C No.11
pp.3796-3802
Special SectionPAPER
System VLSI
An Intelligent Cache Memory Chip Suitable for Logical Inference
Kenichi YASUDA, Kiyohiro FURUTANI, Atsushi MAEDA, Shoichi WAKANO, Hiroshi NAKASHIMA, Yasutaka TAKEDA, Michihiro YAMADA, |
|
Summary | Full Text:PDF | |
| Current List: 41511 - 41520
|
|