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Vol.E74-B No.11
pp.3738-3739 LETTER
Antennas and Propagation A High Efficiency Slotted Array for DBS Reception Using a Copper Clad Laminates Makoto ANDO, Naohisa GOTO, |
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Vol.E74-C No.11
pp.3747-3748 FOREWORD
FOREWORD Osamu TOMISAWA, |
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Vol.E74-C No.11
pp.3749-3756 Special SectionPAPER
Circuit Design A Master Chip Design of 0.5 µm Mixed BiCMOS/CMOS Channelless Gate Array Family Yoji NISHIO, Noriaki OKA, Shigeru TAKAHASHI, Manabu SHIBATA, |
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Vol.E74-C No.11
pp.3757-3765 Special SectionPAPER
Circuit Design Self-Timed Clocking Design for a Data-Driven Microprocessor Fumiyasu ASAI, Shinji KOMORI, Toshiyuki TAMURA, Hisakazu SATO, Hidehiro TAKATA, Yoshihiro SEGUCHI, Takeshi TOKUDA, Hiroaki TERADA, |
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Vol.E74-C No.11
pp.3766-3774 Special SectionPAPER
Core and Macrocells A High Performance 32-Bit Microcontroller for Realtime Applications Masafumi TAKAHASHI, Yasuo YAMADA, Emi KANEKO, Shinichi YOSHIOKA, Haruyuki TAGO, |
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Vol.E74-C No.11
pp.3775-3779 Special SectionPAPER
Core and Macrocells A 64 b CMOS Mainframe Execution Unit Macrocell with Error Detecting Circuit Takehisa HAYASHI, Toshio DOI, Mikio YAMAGISHI, Kazuo KOIDE, Akira ISHIYAMA, Masataka HIRAMATSU, Akira YAMAGIWA, |
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Vol.E74-C No.11
pp.3780-3786 Special SectionPAPER
Core and Macrocells A 5 ns Embedded RAM for CMOS ASICs and Its Applications to a One-Chip 4096-Channel Time Switch VLSI for Digital Switching Systems Masao MIZUKAMI, Yasuo MIKAMI, Osamu MATSUBARA, Yoichi SATOH, Koichi SUDOH, |
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Vol.E74-C No.11
pp.3787-3795 Special SectionPAPER
Core and Macrocells A High-Performance Reconfigurable Line Memory Macrocell for Video Signal Processing ASICs Tetsuya MATSUMURA, Masahiko YOSHIMOTO, Atsushi MAEDA, Yasutaka HORIBA, |
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Vol.E74-C No.11
pp.3796-3802 Special SectionPAPER
System VLSI An Intelligent Cache Memory Chip Suitable for Logical Inference Kenichi YASUDA, Kiyohiro FURUTANI, Atsushi MAEDA, Shoichi WAKANO, Hiroshi NAKASHIMA, Yasutaka TAKEDA, Michihiro YAMADA, |
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Vol.E74-C No.11
pp.3803-3809 Special SectionPAPER
System VLSI The Performance Evaluation of a 64 b Microprocessor with a Two-Level Cache Ryuichi YAMAGUCHI, Joel BONEY, Douglas DUSCHATKO, Tetsuya TANAKA, Jiro MIYAKE, Yoshito NISHIMICHI, Hisakazu EDAMATSU, Shigeru WATARI, Shigeo KUNINOBU, |
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