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Vol.E75-A No.10
pp.1181-1181
FOREWORD
FOREWORD
Kazuhiro UEDA, |
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Vol.E75-A No.10
pp.1182-1190
Special SectionPAPER
Functional Design of a Special Purpose Processor Based on High Level Specification Description
Hironobu KITABATAKE, Katsuhiko SHIRAI, |
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Vol.E75-A No.10
pp.1191-1201
Special SectionPAPER
Optimizing and Scheduling DSP Programs for High Performance VLSI Designs
Frederico Buchholz MACIEL, Yoshikazu MIYANAGA, Koji TOCHINAI, |
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Vol.E75-A No.10
pp.1202-1211
Special SectionPAPER
Algorithms for Multiplexers Assignment after Scheduling and Allocation Steps
Hiroshi SEKIGAWA, Kiyoshi OGURI, Ryo NOMURA, Yukihiro NAKAMURA, |
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Vol.E75-A No.10
pp.1212-1219
Special SectionPAPER
Applications of Boolean Unification to Combinational Logic Synthesis
Yuji KUKIMOTO, Masahiro FUJITA, |
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Vol.E75-A No.10
pp.1220-1229
Special SectionPAPER
Formal Design Verification of Sequential Machines Based on Symbolic Model Checking for Branching Time Regular Temporal Logic
Kiyoharu HAMAGUCHI, Hiromi HIRAISHI, Shuzo YAJIMA, |
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Vol.E75-A No.10
pp.1230-1238
Special SectionPAPER
Timing Verification of Logic Circuits with Combined Delay Model
Shinji KIMURA, Shigemi KASHIMA, Hiromasa HANEDA, |
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Vol.E75-A No.10
pp.1239-1246
Special SectionPAPER
Extraction of Behavioral Descriptions from Synchronous Sequential Circuits
Masahiko OHMURA, Hiroto YASUURA, Keikichi TAMARU, |
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Vol.E75-A No.10
pp.1247-1254
Special SectionPAPER
Coded Time-Symbolic Simulation for Timing Verification of Logic Circuits
Nagisa ISHIURA, Yutaka DEGUCHI, Shuzo YAJIMA, |
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Vol.E75-A No.10
pp.1255-1262
Special SectionPAPER
Parallel Binary Decision Diagram Manipulation
Shinji KIMURA, Tsutomu IGAKI, Hiromasa HANEDA, |
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Current List: 40791 - 40800
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