Warning: Undefined array key "lang" in /var/www/02search_html/bin/search_result.php on line 70

Warning: Undefined array key "input_data" in /var/www/02search_html/bin/search_result.php on line 199

Warning: Undefined array key "Begin_V" in /var/www/02search_html/bin/search_result.php on line 249
IEICE Trans
Search of Paper Information

Search Results

Total 44163 documents match your query. Current List: 40601 - 40610

Vol.E76-C No.3  pp.383-392
INVITED PAPER  
Prospects of Multiple-Valued VLSI Processors
Takahiro HANYU, Michitaka KAMEYAMA, Tatsuo HIGUCHI, 
Summary | Full Text:PDF

Vol.E76-C No.3  pp.393-402
Special SectionPAPER  
Multiple-Valued Memory Using Floating Gate Devices
Takeshi SHIMA, Stephanie RINNERT, 
Summary | Full Text:PDF

Vol.E76-C No.3  pp.403-411
Special SectionPAPER  
Multiple-Valued Static Random-Access-Memory Design and Application
Zheng TANG, Okihiko ISHIZUKA, Hiroki MATSUMOTO, 
Summary | Full Text:PDF

Vol.E76-C No.3  pp.412-418
Special SectionPAPER  
Design of a Multiple-Valued Cellular Array
Naotake KAMIURA, Yutaka HATA, Kazuharu YAMATO, 
Summary | Full Text:PDF

Vol.E76-C No.3  pp.419-427
Special SectionPAPER  
LSI Implementation and Safety Verification of Window Comparator Used in Fail-Safe Multiple-Valued Logic Operations
Masakazu KATO, Masayoshi SAKAI, Koji JINKAWA, Koichi FUTSUHARA, Masao MUKAIDONO, 
Summary | Full Text:PDF

Vol.E76-C No.3  pp.428-435
Special SectionPAPER  
Design of Robust-Fault-Tolerant Multiple-Valued Arithmetic Circuits and Their Evaluation
Takeshi KASUGA, Michitaka KAMEYAMA, Tatsuo HIGUCHI, 
Summary | Full Text:PDF

Vol.E76-C No.3  pp.436-445
Special SectionPAPER  
High Speed MOS Multiplier and Divider Using Redundant Binary Representation and Their Implementation in a Microprocessor
Shigeo KUNINOBU, Tamotsu NISHIYAMA, Takashi TANIGUCHI, 
Summary | Full Text:PDF

Vol.E76-C No.3  pp.446-454
Special SectionPAPER  
VLSI-Oriented Multiple-Valued Current-Mode Arithmetic Circuits Using Redundant Number Representations
Shoji KAWAHITO, Yasuhiro MITSUI, Tetsuro NAKAMURA, 
Summary | Full Text:PDF

Vol.E76-C No.3  pp.455-462
Special SectionPAPER  
Multiple-Valued VLSI Image Processor Based on Residue Arithmetic and Its Evaluation
Makoto HONDA, Michitaka KAMEYAMA, Tatsuo HIGUCHI, 
Summary | Full Text:PDF

Vol.E76-C No.3  pp.463-471
Special SectionPAPER  
Architecture of a Parallel Multiple-Valued Arithmetic VLSI Processor Using Adder-Based Processing Elements
Katsuhiko SHIMABUKURO, Michitaka KAMEYAMA, 
Summary | Full Text:PDF

Current List: 40601 - 40610
go to Page Top