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Vol.E76-C No.11
pp.1589-1594 Special SectionPAPER
DRAM A Smart Design Methodology with Distributed Extra Gate-Arrays for Advanced ULSI Memories Masaki TSUKUDA, Kazutami ARIMOTO, Mikio ASAKURA, Hideto HIDAKA, Kazuyasu FUJISHIMA, |
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Vol.E76-C No.11
pp.1595-1603 Special SectionPAPER
DRAM A Line-Mode Test with Data Register for ULSI Memory Architecture Tsukasa OOISHI, Masaki TSUKUDE, Kazutani ARIMOTO, Yoshio MATSUDA, Kazuyasu FUJISHIMA, |
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Vol.E76-C No.11
pp.1604-1610 Special SectionPAPER
DRAM Minority Carrier Collection in 256 M-bit DRAM Cell on Incidence of Alpha-Particle Analyzed by Three-Dimensional Device Simulation Sumiko OSHIDA, Masao TAGUCHI, |
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Vol.E76-C No.11
pp.1611-1619 Special SectionPAPER
SRAM Noise Reduction Techniques for a 64-kb ECL-CMOS SRAM with a 2-ns Cycle Time Kenichi OHHATA, Yoshiaki SAKURAI, Hiroaki NAMBU, Kazuo KANETANI, Youji IDEI, Toshirou HIRAMOTO, Nobuo TAMBA, Kunihiko YAMAGUCHI, Masanori ODAKA, Kunihiko WATANABE, Takahide IKEDA, Noriyuki HOMMA, |
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Vol.E76-C No.11
pp.1620-1625 Special SectionPAPER
SRAM An Effective Defect-Repair Scheme for a High Speed SRAM Sadayuki OOKUMA, Katsuyuki SATO, Akira IDE, Hideyuki AOKI, Takashi AKIOKA, Hideaki UCHIDA, |
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Vol.E76-C No.11
pp.1626-1631 Special SectionPAPER
Non-volatile Memory Statistical Memory Yield Analysis and Redundancy Design Considering Fabrication Line Improvement Ken-ichi IMAMIYA, Jun-ichi MIYAMOTO, Nobuaki OHTSUKA, Naoto TOMITA, Yumiko IYAMA, |
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Vol.E76-C No.11
pp.1632-1640 Special SectionPAPER
Application Specific Memory Circuit and Functional Design Technologies for 2 Mb VRAM Katsuyuki SATO, Masahiro OGATA, Miki MATSUMOTO, Ryouta HAMAMOTO, Kiichi MANITA, Terutaka OKADA, Yuji SAKAI, Kanji OISHI, Masahiro YAMAMURA, |
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Vol.E76-C No.11
pp.1641-1648 Special SectionPAPER
Application Specific Memory High-Performance Memory Macrocells with Row and Column Sliceable Architecture Nobutaro SHIBATA, Yoshinori GOTOH, Shigeru DATE, |
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Vol.E76-C No.11
pp.1649-1656 Special SectionPAPER
Application Specific Memory A High-Density Multiple-Valued Content-Addressable Memory Based on One Transistor Cell Satoshi ARAGAKI, Takahiro HANYU, Tatsuo HIGUCHI, |
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Vol.E76-C No.11
pp.1657-1664 Special SectionPAPER
Application Specific Memory A Bitline Control Circuit Scheme and Redundancy Technique for High-Density Dynamic Content Addressable Memories Tadato YAMAGATA, Masaaki MIHARA, Takeshi HAMAMOTO, Yasumitsu MURAI, Toshifumi KOBAYASHI, Michihiro YAMADA, Hideyuki OZAKI, |
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