|
Vol.E78-A No.12
pp.1691-1698
Special SectionPAPER
Analysis of Aliasing Probability for MISRs by Using Complete Weight Distributions
Kazuhiko IWASAKI, Sandeep K. GUPTA, Prawat NAGVAJARA, Tadao KASAMI, |
|
Summary | Full Text:PDF | |
|
Vol.E78-A No.12
pp.1699-1706
Special SectionPAPER
"FASTOOL" an FIR Filter Compiler Based on the Automatic Design of the Multi-Input-Adder
Takao YAMAZAKI, Yoshihito KONDO, Sayuri IGOTA, Seiichiro IWASE, |
|
Summary | Full Text:PDF | |
|
Vol.E78-A No.12
pp.1707-1714
Special SectionPAPER
An Instruction Set Optimization Algorithm for Pipelined ASIPs
Nguyen Ngoc BINH, Masaharu IMAI, Akichika SHIOMI, Nobuyuki HIKICHI, |
|
Summary | Full Text:PDF | |
|
Vol.E78-A No.12
pp.1715-1721
Special SectionPAPER
Reclocking Controllers for Minimum Execution Time
Pradip JHA, Sri PARAMESWARAN, Nikil DUTT, |
|
Summary | Full Text:PDF | |
|
Vol.E78-A No.12
pp.1722-1728
Special SectionPAPER
A New Method to Represent Sets of Products: Ternary Decision Diagrams
Koichi YASUOKA, |
|
Summary | Full Text:PDF | |
|
Vol.E78-A No.12
pp.1729-1734
Special SectionPAPER
Implementation Techniques for Fast OBDD Dynamic Variable Reordering
Hiroshige FUJII, |
|
Summary | Full Text:PDF | |
|
Vol.E78-A No.12
pp.1735-1741
Special SectionPAPER
Phase Optimization in Technology Mapping
Yusuke MATSUNAGA, |
|
Summary | Full Text:PDF | |
|
Vol.E78-A No.12
pp.1742-1748
Special SectionPAPER
Conformance Test of a Logic Synthesis System to the Standard HDL UDL/I
Satoshi YOKOTA, Hiroyuki KANBARA, |
|
Summary | Full Text:PDF | |
|
Vol.E78-A No.12
pp.1749-1754
Special SectionPAPER
Validation of UDL/I Test Suites and UDL/I Simulation/Synthesis Environment
Hiroyuki KANBARA, Satoshi YOKOTA, |
|
Summary | Full Text:PDF | |
|
Vol.E78-A No.12
pp.1755-1764
Special SectionPAPER
A CAM-Based Parallel Fault Simulation Algorithm with Minimal Storage Size
Shinsuke OHNO, Masao SATO, Tatsuo OHTSUKI, |
|
Summary | Full Text:PDF | |
|
Current List: 37951 - 37960
|