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Vol.E79-D No.10
pp.1396-1404 Special SectionPAPER
Logic Synthesis Technology Mapping for FPGAs with Composite Logic Block Architectures Hsien-Ho CHUANG, C. Bernard SHUNG, |
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Vol.E79-D No.10
pp.1405-1409 Special SectionPAPER
Lauout Synthesis Delay and Skew Minimized Clock Tree Synthesis for Embedded Arrays Midori TAKANO, Fumihiro MINAMI, Naohito KOJIMA, |
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Vol.E79-D No.10
pp.1410-1418 Special SectionPAPER
Lauout Synthesis An Efficient Timing-Driven Global Routing Method for Standard Cell Layout Tetsushi KOIDE, Takeshi SUZUKI, Shin'ichi WAKABAYASHI, Noriyoshi YOSHIDA, |
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Vol.E79-D No.10
pp.1419-1430 Special SectionPAPER
Lauout Synthesis Mixed Planar and H-V Over-the-Cell Routing for Standard Cells with Nonuniform Over-the-Cell Routing Capacities Tetsushi KOIDE, Shin'ichi WAKABAYASHI, Noriyoshi YOSHIDA, |
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Vol.E79-D No.10
pp.1431-1435 Special SectionPAPER
Design Verification Formal Design Verification of Combinational Circuits Specified by Recurrence Equations Hiroyuki OCHI, Shuzo YAJIMA, |
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Vol.E79-D No.10
pp.1436-1442 Special SectionPAPER
Design for Testability A Partial Scan Design Approach based on Register-Transfer Level Testability Analysis Akira MOTOHARA, Sadami TAKEOKA, Mitsuyasu OHTA, Michiaki MURAOKA, |
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Vol.E79-D No.10
pp.1443-1452 PAPER
Sofware System RTC-Threads: A User-Level Real-Time Threads Package for Multimedia Systems Shuichi OIKAWA, Hideyuki TOKUDA, |
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Vol.E79-D No.10
pp.1453-1461 PAPER
Fault Tolerant Computing Design and Fault Masking of Two-Level Cellular Arrays on Multiple-Valued Logic Naotake KAMIURA, Yutaka HATA, Kazuharu YAMATO, |
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Vol.E79-D No.10
pp.1462-1476 PAPER
Image Processing,Computer Graphics and Pattern Recognition Window-Based Methods for Parameter Estimation of Markov Random Field Images Ken-Chung HO, Bin-Chang CHIEU, |
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Vol.E79-D No.10
pp.1477-1482 LETTER
Image Processing,Computer Graphics and Pattern Recognition A Model-Based Active Landmarks Tracking Method Ronghua YAN, Naoyuki TOKUDA, Juichi MIYAMICHI, |
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Current List: 37171 - 37180
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