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Vol.E80-C No.7
pp.893-898
Special SectionPAPER
Novel Structure Devices
Simulated Device Design Optimization to Reduce the Floating Body Effect for Sub-Quarter Micron Fully Depleted SOI-MOSFETs
Risho KOH, Tohru MOGAMI, Haruo KATO, |
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Summary | Full Text:PDF | |
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Vol.E80-C No.7
pp.899-904
Special SectionPAPER
Novel Structure Devices
A Long Data Retention SOI DRAM with the Body Refresh Function
Shigeki TOMISHIMA, Fukashi MORISHITA, Masaki TSUKUDE, Tadato YAMAGATA, Kazutami ARIMOTO, |
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Summary | Full Text:PDF | |
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Vol.E80-C No.7
pp.905-910
Special SectionPAPER
Novel Structure Devices
An Accurate Model of Fully-Depleted Surrounding Gate Transistor (FD-SGT)
Tetsuo ENDOH, Tairiku NAKAMURA, Fujio MASUOKA, |
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Summary | Full Text:PDF | |
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Vol.E80-C No.7
pp.911-917
Special SectionPAPER
Novel Structure Devices
An Analytic Steady-State Current-Voltage Characteristics of Short Channel Fully-Depleted Surrounding Gate Transistor (FD-SGT)
Tetsuo ENDOH, Tairiku NAKAMURA, Fujio MASUOKA, |
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Summary | Full Text:PDF | |
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Vol.E80-C No.7
pp.918-923
Special SectionPAPER
Novel Concept Devices
Novel Electronic Properties on Ferroelectric/ferromagnetic Heterostructures
Hitoshi TABATA, Tomoji KAWAI, |
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Summary | Full Text:PDF | |
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Vol.E80-C No.7
pp.924-930
Special SectionPAPER
Novel Concept Devices
Low Power Neuron-MOS Technology for High-Functionality Logic Gate Synthesis
Ho-Yup KWON, Koji KOTANI, Tadashi SHIBATA, Tadahiro OHMI, |
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Summary | Full Text:PDF | |
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Vol.E80-C No.7
pp.931-934
Special SectionPAPER
Novel Concept Devices
Design of an Excitable Field Towards a Novel Parallel Computation
Kenichi YOSHIKAWA, Ikuko MOTOIKE, Kimiko KAJIYA, |
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Summary | Full Text:PDF | |
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Vol.E80-C No.7
pp.935-940
Special SectionPAPER
Novel Concept Devices
Design and Analysis of Multiwave Interconnection Networks for MCM-Based Parallel Processing
Takafumi AOKI, Shinichi SHIONOYA, Tatsuo HIGUCHI, |
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Summary | Full Text:PDF | |
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Vol.E80-C No.7
pp.941-947
Special SectionPAPER
Multiple-Valued Architectures
Design and Implementation of a Low-Power Multiple-Valued Current-Mode Integrated Circuit with Current-Source Control
Takahiro HANYU, Satoshi KAZAMA, Michitaka KAMEYAMA, |
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Summary | Full Text:PDF | |
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Vol.E80-C No.7
pp.948-955
Special SectionPAPER
Multiple-Valued Architectures
Design and Evaluation of a 4-Valued Universal-Literal CAM for Cellular Logic Image Processing
Takahiro HANYU, Manabu ARAKAKI, Michitaka KAMEYAMA, |
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Summary | Full Text:PDF | |
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Current List: 36371 - 36380
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