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Vol.E80-A No.10
pp.1820-1825
Special SectionPAPER
Logic Synthesis for Cellular Architecture FPGAs Using EXOR Ternary Decision Diagrams
Gueesang LEE, Sungju PARK, |
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Summary | Full Text:PDF | |
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Vol.E80-A No.10
pp.1826-1833
Special SectionPAPER
ASAver.1: An FPGA-Based Education Board for Computer Architecture/System Design
Hiroyuki OCHI, Yoko KAMIDOI, Hideyuki KAWABATA, |
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Summary | Full Text:PDF | |
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Vol.E80-A No.10
pp.1834-1841
Special SectionPAPER
Top-Down Co-simulation of Hardware/Software Co-designs for Embedded Systems Based Upon a Component Logical Bus Architecture
Katsuhiko SEO, Hisao KOIZUMI, Barry SHACKLEFORD, Mitsuhiro YASUDA, Masashi MORI, Fumio SUZUKI, |
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Summary | Full Text:PDF | |
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Vol.E80-A No.10
pp.1842-1852
Special SectionPAPER
A Co-Evaluation of the Architectures and the CAD System for Speed-Oriented FPGAs
Tsunemasa HAYASHI, Atsushi TAKAHARA, Kennosuke FUKAMI, |
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Summary | Full Text:PDF | |
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Vol.E80-A No.10
pp.1853-1860
Special SectionPAPER
Architecture Evaluation Based on the Datapath Structure and Parallel Constraint
Masayuki YAMAGUCHI, Akihisa YAMADA, Toshihiro NAKAOKA, Takashi KAMBE, Nagisa ISHIURA, |
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Summary | Full Text:PDF | |
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Vol.E80-A No.10
pp.1861-1870
Special SectionPAPER
Routability Analysis of Bit-Serial Pipeline Datapaths
Tsuyoshi ISSHIKI, Wayne Wei-Ming DAI, Hiroaki KUNIEDA, |
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Summary | Full Text:PDF | |
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Vol.E80-A No.10
pp.1871-1877
Special SectionPAPER
On Regular Segmented 2-D FPGA Routing
Yu-Liang WU, Malgorzata MAREK-SADOWSKA, |
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Summary | Full Text:PDF | |
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Vol.E80-A No.10
pp.1878-1882
Special SectionPAPER
Efficient Routability Checking for Global Wires in Planar Layouts
Naoyuki ISO, Yasushi KAWAGUCHI, Tomio HIRATA, |
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Summary | Full Text:PDF | |
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Vol.E80-A No.10
pp.1883-1891
Special SectionPAPER
A Two-Dimensional Transistor Placement Algorithm for Cell Synthesis and Its Application to Standard Cells
Shunji SAIKA, Masahiro FUKUI, Noriko SHINOMIYA, Toshiro AKINO, Shigeo KUNINOBU, |
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Summary | Full Text:PDF | |
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Vol.E80-A No.10
pp.1892-1901
Special SectionPAPER
A New Description of MOS Circuits at Switch-Level with Applications
Massoud PEDRAM, Xunwei WU, |
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Summary | Full Text:PDF | |
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