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Vol.E80-A No.10
pp.1742-1748
Special SectionPAPER
An XOR-Based Decomposition Diagram and Its Application in Synthesis of AND/XOR Networks
Yibin YE, Kaushik ROY, |
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Summary | Full Text:PDF | |
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Vol.E80-A No.10
pp.1749-1755
Special SectionPAPER
The Controlling Value Boolean Matching
Ricardo FERREIRA, Anne-Marie TRULLEMANS, Qinhai ZHANG, |
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Summary | Full Text:PDF | |
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Vol.E80-A No.10
pp.1756-1766
Special SectionPAPER
Combining Architectural Simulation and Behavioral Synthesis
Abderrazak JEMAI, Polen KISSION, Ahmed Amine JERRAYA, |
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Summary | Full Text:PDF | |
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Vol.E80-A No.10
pp.1767-1773
Special SectionPAPER
A Hierarchical Clustering Method for the Multiple Constant Multiplication Problem
Akihiro MATSUURA, Mitsuteru YUKISHITA, Akira NAGOYA, |
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Summary | Full Text:PDF | |
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Vol.E80-A No.10
pp.1774-1781
Special SectionPAPER
Manipulation of Large-Scale Polynomials Using BMDs
Dror ROTTER, Kiyoharu HAMAGUCHI, Shin-ichi MINATO, Shuzo YAJIMA, |
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Summary | Full Text:PDF | |
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Vol.E80-A No.10
pp.1782-1788
Special SectionPAPER
Path Mapping: Delay Estimation for Technology Independent Synthesis
Yutaka TAMIYA, |
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Summary | Full Text:PDF | |
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Vol.E80-A No.10
pp.1789-1794
Special SectionPAPER
Delay Calculation Method for SRAM-based FPGAs
Masaru KATAYAMA, Atsushi TAKAHARA, Toshiaki MIYAZAKI, Kennosuke FUKAMI, |
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Summary | Full Text:PDF | |
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Vol.E80-A No.10
pp.1795-1806
Special SectionPAPER
A performance-Oriented Simultaneous Placement and Global Routing Algorithm for Transport-Processing FPGAs
Nozomu TOGAWA, Masao SATO, Tatsuo OHTSUKI, |
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Summary | Full Text:PDF | |
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Vol.E80-A No.10
pp.1807-1812
Special SectionPAPER
An Efficient FPGA Technology Mapping Tightly Coupled with Logic Minimization
Kang YI, Seong Yong OHM, Chu Shik JHON, |
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Summary | Full Text:PDF | |
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Vol.E80-A No.10
pp.1813-1819
Special SectionPAPER
A Variable Partitioning Algorithm of BDD for FPGA Technology Mapping
Jie-Hong JIANG, Jing-Yang JOU, Juinn-Dar HUANG, Jung-Shian WEI, |
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Summary | Full Text:PDF | |
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Current List: 36091 - 36100
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