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IEICE Trans

Keyword : test architecture design

Thermal-Aware Test Access Mechanism and Wrapper Design Optimization for System-on-Chips
Thomas Edison YU Tomokazu YONEDA Krishnendu CHAKRABARTY Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/10/01
Vol. E91-D  No. 10 ; pp. 2440-2448
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
SoC testing, test architecture design, test scheduling, thermal constraint, 
 Summary | Full Text:PDF