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IEICE Trans

Keyword : load-use hazard

Hiding Data Cache Latency with Load Address Prediction
Toshinori SATO Hiroshige FUJII Seigo SUZUKI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/11/25
Vol. E79-D  No. 11 ; pp. 1523-1532
Type of Manuscript:  PAPER
Category: Computer Systems
Keyword: 
RISC, cache memory, load-use hazard, load latency, address prediction, 
 Summary | Full Text:PDF