Seigo SUZUKI


Hiding Data Cache Latency with Load Address Prediction
Toshinori SATO Hiroshige FUJII Seigo SUZUKI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/11/25
Vol. E79-D  No. 11  pp. 1523-1532
Type of Manuscript:  PAPER
Category: Computer Systems
Keyword: 
RISCcache memoryload-use hazardload latencyaddress prediction
 Summary | Full Text:PDF

Performance Evaluation of a Processing Element for an On-Chip Multiprocessor
Masafumi TAKAHASHI Hiroshige FUJII Emi KANEKO Takeshi YOSHIDA Toshinori SATO Hiroyuki TAKANO Haruyuki TAGO Seigo SUZUKI Nobuyuki GOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/07/25
Vol. E77-C  No. 7  pp. 1092-1100
Type of Manuscript:  Special Section PAPER (Special Issue on Super Chip for Intelligent Integrated Systems)
Category: 
Keyword: 
multiprocessorshared FPUon-chip cacheprefetch
 Summary | Full Text:PDF