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IEICE Trans

Keyword : diagnostic rules

Multiple Gate Delay Fault Diagnosis Using Test-Pairs for Marginal Delays
Kwame Osei BOATENG Hiroshi TAKAHASHI Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/07/25
Vol. E81-D  No. 7 ; pp. 706-715
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Diagnosis of VLSI)
Category: Fault Diagnosis
Keyword: 
combinational circuit, fault diagnosis, multiple delay fault, diagnostic rules, path-tracing method, test-pairs for marginal delays, 
 Summary | Full Text:PDF