Kwame Osei BOATENG


Design of C-Testable Modified-Booth Multipliers
Kwame Osei BOATENG Hiroshi TAKAHASHI Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2000/10/25
Vol. E83-D  No. 10  pp. 1868-1878
Type of Manuscript:  PAPER
Category: Fault Tolerance
Keyword: 
multipliermodified Booth Algorithmdesign for testability (DFT)C-testable design
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Diagnosing Delay Faults in Combinational Circuits Under the Ambiguous Delay Model
Kwame Osei BOATENG Hiroshi TAKAHASHI Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1999/12/25
Vol. E82-D  No. 12  pp. 1563-1571
Type of Manuscript:  PAPER
Category: Fault Tolerant Computing
Keyword: 
combinational circuitambiguous delay modelmultiple fault diagnosispath-tracing method
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A Method of Generating Tests with Linearity Property for Gate Delay Faults in Combinational Circuits
Hiroshi TAKAHASHI Kwame Osei BOATENG Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1999/11/25
Vol. E82-D  No. 11  pp. 1466-1473
Type of Manuscript:  PAPER
Category: Fault Tolerant Computing
Keyword: 
combinational circuitmarginal chipgate delay faulttest generationtest with linearity property
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Multiple Gate Delay Fault Diagnosis Using Test-Pairs for Marginal Delays
Kwame Osei BOATENG Hiroshi TAKAHASHI Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/07/25
Vol. E81-D  No. 7  pp. 706-715
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Diagnosis of VLSI)
Category: Fault Diagnosis
Keyword: 
combinational circuitfault diagnosismultiple delay faultdiagnostic rulespath-tracing methodtest-pairs for marginal delays
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