A Delay Model of Multiple-Valued Logic Circuits Consisting of Min, Max, and Literal Operations Noboru TAKAGI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2010/08/01 Vol. E93-DNo. 8 ;
pp. 2040-2047 Type of Manuscript: Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing) Category: Logic Design Keyword: multiple-valued logic, multiple-valued logic circuits, hazard detection, delay model,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1994/12/25 Vol. E77-ANo. 12 ;
pp. 2058-2066 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: global routing, timing driven layout, bipolar LSI, delay model, routing graph, critical path,