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IEICE Trans

Keyword : boundary scan

On Detecting Delay Faults Using Time-to-Digital Converter Embedded in Boundary Scan
Hiroyuki YOTSUYANAGI Hiroyuki MAKIMOTO Takanobu NIMIYA Masaki HASHIZUME 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/09/01
Vol. E96-D  No. 9 ; pp. 1986-1993
Type of Manuscript:  Special Section PAPER (Special Section on Dependable Computing)
Category: 
Keyword: 
delay testing, time-to-digital converter, boundary scan, design for testability, 
 Summary | Full Text:PDF
Complete Diagnosis Patterns for Wiring Interconnects
Sungju PARK Gueesang LEE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/04/25
Vol. E81-A  No. 4 ; pp. 672-676
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
boundary scan, shorted nets fault, stuck-at fault, fault detection, fault diagnosis, interconnect test, 
 Summary | Full Text:PDF