Complete Diagnosis Patterns for Wiring Interconnects

Sungju PARK  Gueesang LEE  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E81-A   No.4   pp.672-676
Publication Date: 1998/04/25
Online ISSN: 
Print ISSN: 0916-8508
Type of Manuscript: PAPER
Category: VLSI Design Technology and CAD
boundary scan,  shorted nets fault,  stuck-at fault,  fault detection,  fault diagnosis,  interconnect test,  

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It is important to test the various kinds of interconnect faults between chips on a card/module. When boundary scan design techniques are adopted, the chip to chip interconnection test generation and application of test patterns is greatly simplified. Various test generation algorithms have been developed for interconnect faults. A new interconnect test generation algorithm is introduced. It reduces the number of test patterns by half over present techniques. It also guarantees the complete diagnosis of multiple interconnect faults.