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IEICE Trans

Keyword : annealing processor

A Fully-Parallel Annealing Algorithm with Autonomous Pinning Effect Control for Various Combinatorial Optimization Problems
Daiki OKONOGI Satoru JIMBO Kota ANDO Thiem Van CHU Jaehoon YU Masato MOTOMURA Kazushi KAWAMURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2023/12/01
Vol. E106-D  No. 12 ; pp. 1969-1978
Type of Manuscript:  Special Section PAPER (Special Section on Forefront Computing)
Category: 
Keyword: 
combinatorial optimization, Ising model, annealing processor, parallel annealing algorithm, stochastic cellular automata, 
 Summary | Full Text:PDF
FPGA-Based Annealing Processor with Time-Division Multiplexing
Kasho YAMAMOTO Masayuki IKEBE Tetsuya ASAI Masato MOTOMURA Shinya TAKAMAEDA-YAMAZAKI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2019/12/01
Vol. E102-D  No. 12 ; pp. 2295-2305
Type of Manuscript:  Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: Computer System
Keyword: 
ising model, annealing processor, simulated annealing, 
 Summary | Full Text:PDF