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IEICE Trans

Keyword : STT-RAM

Write Avoidance Cache Coherence Protocol for Non-volatile Memory as Last-Level Cache in Chip-Multiprocessor
Ju Hee CHOI Jong Wook KWAK Chu Shik JHON 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/08/01
Vol. E97-D  No. 8 ; pp. 2166-2169
Type of Manuscript:  LETTER
Category: Computer System
Keyword: 
cache coherence, non volatile memory, STT-RAM, chip multi-processor, 
 Summary | Full Text:PDF