Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/10/01 Vol. E93-ANo. 10 ;
pp. 1775-1781 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: FPGA, Boolean matching, Bloom filter, SAT, re-synthesis,
Efficient Computation of Canonical Form under Variable Permutation and Negation for Boolean Matching in Large Libraries Debatosh DEBNATHTsutomu SASAO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/12/01 Vol. E89-ANo. 12 ;
pp. 3443-3450 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis Keyword: logic synthesis, Boolean matching, cell-library binding, technology mapping, canonical form,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/12/01 Vol. E87-ANo. 12 ;
pp. 3134-3140 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis Keyword: Boolean matching, technology mapping, variable permutation, P-equivalence,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/10/25 Vol. E80-ANo. 10 ;
pp. 1749-1755 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: Boolean matching, observability, technology mapping, signatures,
A New Algorithm for Boolean Matching Utilizing Structural Information Yusuke MATSUNAGA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1995/03/25 Vol. E78-DNo. 3 ;
pp. 219-223 Type of Manuscript: Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design) Category: Logic Synthesis Keyword: logic synthesis, technology mapping, Boolean matching, binary decision diagrams,