Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2003/04/01
Vol. E86-C
No. 4 ;
pp. 580-588
Type of Manuscript:
Special Section PAPER (Special Issue on High-Performance, Low-Power System LSIs and Related Technologies)
Category: Architecture and Algorithms
Keyword:
processor architecture, cache, on-chip memory, way activation, memory traffic, |