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IEICE Trans

Keyword : variable-width-bus scheme

Partitioned-Bus and Variable-Width-Bus Scheme for Low Power Digital Processors
Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/03/25
Vol. E79-C  No. 3 ; pp. 424-429
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
low power, partitioned-bus architecture, variable-width-bus scheme, microprocessor, 
 Summary | Full Text:PDF