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Design of a 3.2 GHz 50 mW 0.5 µm GaAs PLL-Based Clock Generator with 1 V Power Supply
Tadayoshi ENOMOTO Toshiyuki OKUYAMA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1994/12/25
Vol. E77-C
No. 12 ;
pp. 1957-1965
Type of Manuscript:
Special Section PAPER (Special Issue on Multimedia, Analog and Processing LSIs)
Category: Processor Interfaces
Keyword:
phase-locked loop (PLL), clock pulse generator (CG), voltage controlled ring oscillater (VCO), VCO gain, GaAs, MESFET, DCFL circuit, pull-in frequency, pull-in range, pull-in time, lock range, lock time, locked state, | | | Summary | Full Text:PDF | |
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