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IEICE Trans

Keyword : on-chip cache

Utilization of the On-Chip L2 Cache Area in CC-NUMA Multiprocessors for Applications with a Small Working Set
Sung Woo CHUNG Hyong-Shik KIM Chu Shik JHON 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/07/01
Vol. E87-D  No. 7 ; pp. 1617-1624
Type of Manuscript:  Special Section PAPER (Special Section on Hardware/Software Support for High Performance Scientific and Engineering Computing)
Category: Networking and System Architectures
Keyword: 
CC-NUMA multiprocessor, cache replacement policy, on-chip cache, remote victim cache, distance-aware cache, interconnection network, 
 Summary | Full Text:PDF
A Virtual Cache Architecture for Retaining the Process Working Sets in a Multiprogramming Environment
Dongwook KIM Joonwon LEE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/12/25
Vol. E79-D  No. 12 ; pp. 1637-1645
Type of Manuscript:  PAPER
Category: Computer Hardware and Design
Keyword: 
virtual cache, conflict miss, multiprogramming, context switch, on-chip cache, 
 Summary | Full Text:PDF
Performance Evaluation of a Processing Element for an On-Chip Multiprocessor
Masafumi TAKAHASHI Hiroshige FUJII Emi KANEKO Takeshi YOSHIDA Toshinori SATO Hiroyuki TAKANO Haruyuki TAGO Seigo SUZUKI Nobuyuki GOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/07/25
Vol. E77-C  No. 7 ; pp. 1092-1100
Type of Manuscript:  Special Section PAPER (Special Issue on Super Chip for Intelligent Integrated Systems)
Category: 
Keyword: 
multiprocessor, shared FPU, on-chip cache, prefetch, 
 Summary | Full Text:PDF