Toshinori SATO


Trading Accuracy for Power with a Configurable Approximate Adder
Toshinori SATO Tongxin YANG Tomoaki UKEZONO 
Publication:   
Publication Date: 2019/04/01
Vol. E102-C  No. 4  pp. 260-268
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
approximate computinglow-power circuitapproximate adder
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Design and Analysis of Approximate Multipliers with a Tree Compressor
Tongxin YANG Tomoaki UKEZONO Toshinori SATO 
Publication:   
Publication Date: 2019/03/01
Vol. E102-A  No. 3  pp. 532-543
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
approximate computingapproximate tree compressorhigh speed multiplierlow power multipliersmall area multiplier
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Design and Analysis of A Low-Power High-Speed Accuracy-Controllable Approximate Multiplier
Tongxin YANG Tomoaki UKEZONO Toshinori SATO 
Publication:   
Publication Date: 2018/12/01
Vol. E101-A  No. 12  pp. 2244-2253
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
approximate computingaccuracy-controllable multiplierlow-power multiplierhigh-speed multiplier
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Short Term Cell-Flipping Technique for Mitigating SNM Degradation Due to NBTI
Yuji KUNITAKE Toshinori SATO Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/04/01
Vol. E94-C  No. 4  pp. 520-529
Type of Manuscript:  Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
Category: 
Keyword: 
NBTISRAMstatic noise marginstress probabilityregister filecache memory
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Enhancements of a Circuit-Level Timing Speculation Technique and Their Evaluations Using a Co-simulation Environment
Yuji KUNITAKE Kazuhiro MIMA Toshinori SATO Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/04/01
Vol. E92-C  No. 4  pp. 483-491
Type of Manuscript:  Special Section PAPER (Special Section on Low-Leakage, Low-Voltage, Low-Power and High-Speed Technologies for System LSIs in Deep-Submicron Era)
Category: 
Keyword: 
worst-case designtiming errorco-simulationparameter variation
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A Simple Mechanism for Collapsing Instructions under Timing Speculation
Toshinori SATO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/09/01
Vol. E91-C  No. 9  pp. 1394-1401
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Processors Based on Novel Concepts in Computation)
Category: 
Keyword: 
typical-case designconstructive timing violationinstruction collapsing
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A Low-Power Instruction Issue Queue for Microprocessors
Shingo WATANABE Akihiro CHIYONOBU Toshinori SATO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/04/01
Vol. E91-C  No. 4  pp. 400-409
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories)
Category: 
Keyword: 
microprocessorsinstruction schedulingCAMRAMlow-power
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An Energy-Efficient Clustered Superscalar Processor
Toshinori SATO Akihiro CHIYONOBU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/04/01
Vol. E88-C  No. 4  pp. 544-551
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP)
Category: Digital
Keyword: 
low power architectureenergy reductionclustered processorsdual-voltage pipelinecritical path prediction
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A Transparent Transient Faults Tolerance Mechanism for Superscalar Processors
Toshinori SATO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/12/01
Vol. E86-D  No. 12  pp. 2508-2516
Type of Manuscript:  Special Section PAPER (Special Issue on Dependable Computing)
Category: Dependable Systems
Keyword: 
fault-tolerancetime redundancytransient faultsinstruction level parallelisminstruction reissue
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Potential of Constructive Timing-Violation
Toshinori SATO Itsujiro ARITA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/02/01
Vol. E85-C  No. 2  pp. 323-330
Type of Manuscript:  Special Section PAPER (Special Issue on High-Performance and Low-Power Microprocessors)
Category: High-Performance Technologies
Keyword: 
instruction level parallelismlow power designfault tolerancetiming constraintsspeculative execution
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A Microprocessor Architecture Utilizing Histories of Dynamic Sequences Saved in Distributed Memories
Toshinori SATO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/09/25
Vol. E81-C  No. 9  pp. 1398-1407
Type of Manuscript:  Special Section PAPER (Special Issue on Novel VLSI Processor Architectures)
Category: 
Keyword: 
instruction level parallelismsuperscalar processorsout-of-order executionnon-consecutive basic block bufferdynamic speculation of data dependence
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Resolving Load Data Dependency Using Tunneling-Load Technique
Toshinori SATO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/08/25
Vol. E81-D  No. 8  pp. 829-838
Type of Manuscript:  PAPER
Category: Computer Systems
Keyword: 
load latencyload address predictionload address generationsuperscalar processorsILP
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Hiding Data Cache Latency with Load Address Prediction
Toshinori SATO Hiroshige FUJII Seigo SUZUKI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/11/25
Vol. E79-D  No. 11  pp. 1523-1532
Type of Manuscript:  PAPER
Category: Computer Systems
Keyword: 
RISCcache memoryload-use hazardload latencyaddress prediction
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Performance Evaluation of a Processing Element for an On-Chip Multiprocessor
Masafumi TAKAHASHI Hiroshige FUJII Emi KANEKO Takeshi YOSHIDA Toshinori SATO Hiroyuki TAKANO Haruyuki TAGO Seigo SUZUKI Nobuyuki GOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/07/25
Vol. E77-C  No. 7  pp. 1092-1100
Type of Manuscript:  Special Section PAPER (Special Issue on Super Chip for Intelligent Integrated Systems)
Category: 
Keyword: 
multiprocessorshared FPUon-chip cacheprefetch
 Summary | Full Text:PDF